公开(公告)号：CA945690A

公开(公告)日：1974-04-16

申请号：CA85321

申请日：1970-06-12

Applicant: IBM

Inventor： BERENBAUM LEONARD ,  ROSENBERG ROBERT ,  TOTTA PAUL A

IPC: H05K3/24 ,  H01B1/02 ,  H01L21/00 ,  H01L21/28 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/43

公开(公告)号：CA1126629A

公开(公告)日：1982-06-29

申请号：CA348144

申请日：1980-03-21

Applicant: IBM

Inventor： ROTHMAN LAURA B ,  TOTTA PAUL A ,  WHITE JAMES F

IPC: H01L21/306 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L23/485 ,  H01L21/283

Abstract: A method for forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask in an inverse vertical relationship with the desired metal film. The method involves the preliminary blanket deposition of the metal in-point, followed by a coating of a patterned lift-off mask over which is blanket coated a dryetch resistant material with subsequent removal of the lift-off mask, and dry etching of the exposed metal film. In one embodiment the dry-etch mask can comprise a diverse metal layer when a dry-etch ambient is employed which is passive to the d;verse metal. In another embodiment, where dry etch ambients are employed which are corrosive to the diverse metal which is desired in the final structure, it can be covered with a blanket layer of any convenient dry-etch resistant material, such as magnesium oxide, prior to removal of the lift-off mask. This method has effective application in the fabrication of Schottky barrier diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal to semiconductor junctions or interfaces.

公开(公告)号：CA824347A

公开(公告)日：1969-09-30

申请号：CA824347D

Applicant: IBM

Inventor： KARAN CLARENCE ,  DEWITT DAVID ,  NAPIER JOHN ,  SOPHER RAEMAN P ,  TOTTA PAUL A

公开(公告)号：CA2084685A1

公开(公告)日：1991-12-20

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA869649A

公开(公告)日：1971-04-27

申请号：CA869649D

Applicant: IBM

Inventor： SEELEY GERARD ,  TOTTA PAUL A ,  WALD GEORGE

公开(公告)号：CA2009247A1

公开(公告)日：1990-10-17

申请号：CA2009247

申请日：1990-02-02

Applicant: IBM

Inventor： RODBELL KENNETH P ,  TOTTA PAUL A ,  WHITE JAMES F

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/16 ,  H05K3/38

Abstract: A sputtered low copper concentration multilayered device interconnect metallurgy structure is disclosed herein. The interconnect metallurgy is seen to comprise a four-layer structure over an interplanar stud connection (10) surrounded by an insulator (8) to make connection to a device substrate (6). The four-layer structure consists of an intermetallic bottom layer (12 min ) typically 700 ANGSTROM thick and, in a preferred embodiment would comprise TiAl3. Above is a low percent (

公开(公告)号：CA1093699A

公开(公告)日：1981-01-13

申请号：CA285781

申请日：1977-08-30

Applicant: IBM

Inventor： KOOPMAN NICHOLAS G ,  TOTTA PAUL A

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433 ,  H05K1/04 ,  H05K3/10

Abstract: A circuit package exhibiting an excellent heat transfer path from a semiconductor chip or other heat-generating device to the heat-sink can or cover of the package. A heat-conducting pad is metallurgically bonded to either said cover or a surface of said device; the pad is also separably attached, but metallurgically unbonded, to the other. In one preferred embodiment, a readily deformable metal or alloy, such as indium, is metallurgically bonded to a limited central region of the heat sink cover. The deformable metal is separably attached to a major surface of the chip so that there is no stress between the chip or its joints and the solder during the electrical operation of the chip when it generates heat. The preferred method of fabrication involves the mechanical deformation of a mass of solder against the back side of the chip, after the solder has been metallurgically bonded to heat sink. The process may be accomplished either at high or low temperatures, depending upon the solder composition and the relative strength of the leads which join the chip to conductive lands on its supportive substrate.

公开(公告)号：CA859935A

公开(公告)日：1970-12-29

申请号：CA859935D

Applicant: IBM

Inventor： TOTTA PAUL A ,  MUTTER WALTER E

公开(公告)号：CA2084685C

公开(公告)日：1996-01-16

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/488 ,  H01L23/50

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA1277435C

公开(公告)日：1990-12-04

申请号：CA570925

申请日：1988-06-30

Applicant: IBM

Inventor： GAJDA JOSEPH J ,  SRIKRISHNAN KRIS V ,  TOTTA PAUL A ,  TRUDEAU FRANCIS G

IPC: H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/90

Abstract: Chip Contacts Without Opens An integrated circuit chip including a first and a higher second surface levels with an abrupt sidewall step transition therebetween, and having a first layer of a first conductive material disposed over the first surface level and over the second surface level, but terminating on the first surface level in a first end portion which extends up to but does not touch the sidewall. This end portion comprises a conductive material which has been converted to an insulator. A second layer of a second conductive material is disposed on top of the first conductive layer with essentially no conductive material conversion to insulator therein adjacent to the abrupt sidewall transition. In a preferred embodiment, the conductive material is an alloy of aluminum and the end portion is aluminum oxide.