公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：WO2007044324A2

公开(公告)日：2007-04-19

申请号：PCT/US2006038593

申请日：2006-10-02

Applicant: IBM ,  YANG HAINING

Inventor： YANG HAINING

IPC: H01L21/336 ,  H01L29/772

CPC classification number: H01L21/823425 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

Abstract translation: 用于形成用于半导体器件的非对称间隔结构的方法包括在设置在半导体衬底上的至少一对相邻间隔开的栅极结构上形成间隔层。 栅极结构间隔开，使得间隔层在栅极结构之间的区域中以第一厚度形成，并且在其它位置处形成第二厚度，第二厚度大于所述第一厚度。 蚀刻间隔层以便形成用于一对相邻隔开的栅极结构的非对称间隔结构。

公开(公告)号：WO2008051674A3

公开(公告)日：2008-08-28

申请号：PCT/US2007079375

申请日：2007-09-25

Applicant: IBM ,  YANG CHIH-CHAO ,  YANG HAINING

Inventor： YANG CHIH-CHAO ,  YANG HAINING

IPC: G11C17/14

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a trench feature in a substrate, depositing fuse material in the trench feature and compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract translation: 半导体熔丝包括熔丝元件和减小熔丝元件的电迁移电阻的压应力衬垫。 该方法包括在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料并将压应力衬垫材料沉积在熔丝材料上，以及对压应力衬垫材料进行图案化。

公开(公告)号：WO2004088726A3

公开(公告)日：2004-11-25

申请号：PCT/EP2004003540

申请日：2004-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  FAYAZ FAZIL MOHAMMED ,  KERST UWE ,  MEZZAPELLE JOSEPH ,  YANG HAINING

Inventor： FAYAZ FAZIL MOHAMMED ,  KERST UWE ,  MEZZAPELLE JOSEPH ,  YANG HAINING

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/92

CPC classification number: H01L28/40 ,  H01L27/0805

Abstract: A MIM capacitor includes a bottom plate (212), a capacitor dielectric (214) disposed over the bottom plate, and a top plate (216) disposed over the capacitor dielectric. An etch stop material (218) is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist (220) used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges (224) beneath the etch stop material.

Abstract translation: MIM电容器包括底板（212），设置在底板上的电容器电介质（214）和设置在电容器电介质上的顶板（216）。 蚀刻停止材料（218）设置在顶板上方，并且顶板的宽度小于蚀刻停止材料宽度的宽度。 在去除用于图案化顶板的抗蚀剂（220）期间，顶板边缘可以被拉回，通过在抗蚀剂蚀刻中添加适于将下面的顶板边缘（224）拉回或倒下的化学物质 蚀刻停止材料。

公开(公告)号：AU2003296359A1

公开(公告)日：2005-07-21

申请号：AU2003296359

申请日：2003-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING ,  BUEHRER FREDERICK WILLIAM

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：AU2003298347A1

公开(公告)日：2004-06-30

申请号：AU2003298347

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  TULIPE DOUGLAS JR LA ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：AT441938T

公开(公告)日：2009-09-15

申请号：AT06830385

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  HSU LOUIS ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：DE60332865D1

公开(公告)日：2010-07-15

申请号：DE60332865

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

公开(公告)号：AT470237T

公开(公告)日：2010-06-15

申请号：AT03796085

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.