公开(公告)号：WO2008039166A2

公开(公告)日：2008-04-03

申请号：PCT/US2006028464

申请日：2006-07-21

Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/16 ,  G11C2213/77 ,  Y10S977/742 ,  Y10S977/939 ,  Y10S977/943

Abstract: Non-volatile and radiation-hard switching and memory devices (225) using vertical nano-tubes (155) and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract translation: 使用垂直纳米管（155）的非易失性和辐射硬的开关和存储器件（225）并且通过范德华力力可逆地保持状态和制造器件的方法。 用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。

公开(公告)号：WO2005069372A8

公开(公告)日：2005-11-03

申请号：PCT/US0340295

申请日：2003-12-18

Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract translation: 沟槽型存储器件包括在衬底（100）中的沟槽，衬有沟槽的碳纳米管束（202）和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成沟槽衬里的开放柱状结构。 该装置通过在基底上提供碳纳米管催化剂结构并在基底中图案化沟槽而形成; 然后将碳纳米管向下生长到沟槽中以将沟槽与碳纳米管束对齐，之后用沟槽导体填充沟槽。

公开(公告)号：WO03019671A3

公开(公告)日：2003-04-10

申请号：PCT/US0228265

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

Abstract translation: 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻形成的半导体柱（2910）的相对侧的潜在独立的栅极结构（3230）。 栅极结构由绝缘材料（2620）包围，其被选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，将一个触点（3820）制成在支柱的下端。 柱的上端由盖​​（2730）和选择性可蚀刻材料的侧壁覆盖，使得栅极和源极连接开口（3720,3620）也可以通过具有良好配准公差的选择性蚀刻制成。

公开(公告)号：WO2007106855A2

公开(公告)日：2007-09-20

申请号：PCT/US2007063977

申请日：2007-03-14

Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W

IPC: F15C1/06

CPC classification number: F15C1/06 ,  F04B43/043 ,  F15C5/00 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0051 ,  F16K2099/0074 ,  F16K2099/0094 ,  Y10T29/49236 ,  Y10T29/49412 ,  Y10T137/2224

Abstract: Micro-valves (257) and micro-pumps (400) and methods of fabricating micro- valves (257) and micro-pumps (400). The micro-valves (257) and micro-pumps (400) include electrically conductive diaphragms (155) fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves (257) and pumping action of the micro-pumps (400) is accomplished by applying electrostatic forces to the electrically conductive diaphragms (155).

Abstract translation: 微型阀（257）和微型泵（400）以及微型阀（257）和微型泵（400）的制造方法。 微阀（257）和微泵（400）包括由导电纳米纤维制成的导电隔膜（155）。 通过对导电隔膜（155）施加静电力来实现通过微型阀（257）的流体流动和微型泵（400）的泵送作用。

公开(公告)号：WO2006076377A2

公开(公告)日：2006-07-20

申请号：PCT/US2006000844

申请日：2006-01-10

Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: H01L21/3205

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Conductive sidewall spacer stractures are formed using a method tiiat patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract translation: 导电侧壁间隔物结构使用方法（图案）结构（心轴）形成并激活结构的侧壁。 金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。 然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

公开(公告)号：WO03025977A3

公开(公告)日：2003-08-14

申请号：PCT/US0230369

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

Abstract translation: 本发明涉及包括具有上表面和彼此相对的第一和第二侧表面的衬底的缠绕栅极晶体管。 源极和漏极区域（28）形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 栅极电介质层（40）形成在衬底上。 栅极电极（42）形成在栅极电介质层（40）上，以从上表面和第一和第二侧表面覆盖沟道区域，栅电介质（40）位于它们之间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛（12），并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域（28）形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

公开(公告)号：DE602005027316D1

公开(公告)日：2011-05-19

申请号：DE602005027316

申请日：2005-02-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES WILLIAM ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/05 ,  G11C13/02 ,  H01L21/335 ,  H01L21/336 ,  H01L27/28 ,  H01L29/06 ,  H01L29/12 ,  H01L29/772 ,  H01L51/30 ,  H01L51/40

公开(公告)号：CA2559219C

公开(公告)日：2010-11-02

申请号：CA2559219

申请日：2005-03-22

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  KOBURGER CHARLES WILLIAM III ,  SLINKMAN JAMES ALBERT

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

公开(公告)号：DE60233872D1

公开(公告)日：2009-11-12

申请号：DE60233872

申请日：2002-05-30

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

IPC: H01L21/76 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.

公开(公告)号：AT444567T

公开(公告)日：2009-10-15

申请号：AT02735604

申请日：2002-05-30

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

IPC: H01L21/76 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.