公开(公告)号：DE10111803A1

公开(公告)日：2002-06-27

申请号：DE10111803

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  LUETZEN JOERN

IPC: C25D7/12 ,  H01L21/288 ,  H01L21/3063 ,  H01L21/60

Abstract: Arrangement for contacting a semiconductor substrate comprises a substrate (1) having a first main surface (2) lying opposite a second main surface (3); a conducting layer (5) arranged on the first main surface; a first conducting layer (6) arranged on the conducting layer; and a first contact needle (10) inserted through the first insulating layer up to the conducting layer. An Independent claim is also included for a process for contacting a semiconductor substrate. Preferred Features: A second contact needle (11) is inserted through the first insulating layer up to the conducting layer. The first contact needle has a first electrical connection (12) and forms an electrical connection between the conducting layer and the electrical connection. A barrier layer (4) is arranged between the substrate and the conducting layer.

公开(公告)号：DE10027931C1

公开(公告)日：2002-01-10

申请号：DE10027931

申请日：2000-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  LUETZEN JOERN

IPC: H01L21/683 ,  H01L21/3063 ,  H01L21/28 ,  H01L21/68

公开(公告)号：DE59712601D1

公开(公告)日：2006-05-11

申请号：DE59712601

申请日：1997-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  WENDT HERMANN ,  WILLER JOSEF ,  LEHMANN VOLKER ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  KRAUTSCHNEIDER WOLFGANG ,  HOFMANN FRANZ

IPC: H01L21/8247 ,  H01L29/792 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788

Abstract: The invention concerns a non-volatile storage cell having a MOS transistor which, as gate dielectric, comprises a triple dielectric layer (5) consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The MOS transistor gate electrode comprises p -doped silicon such that, when a negative voltage is applied to the gate electrode, holes tunnel predominantly from the channel area (4) through the first silicon oxide layer (51) and into the silicon nitride layer (52).

公开(公告)号：DE10315068B3

公开(公告)日：2004-08-05

申请号：DE10315068

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81C1/00 ,  H01L21/68 ,  H01L21/306 ,  H01L21/311 ,  H01L21/58

Abstract: The sacrificial layer removal method has microchannels formed in at least one structured layer between a first substrate and a second substrate provided with a sacrificial layer, with full or partial insertion of the substrate arrangement (2) in a housing (1) having an entry opening (10) at one end and an exit opening (11) at the opposite end. A seal is provided between the exit opening and the substrate arrangement and the entry opening is supplied with a sacrificial layer removal medium, the microchannels used for supplying it to the sacrificial layer. An independent claim for a sacrificial layer removal device is also included.

公开(公告)号：DE10162983A1

公开(公告)日：2003-07-10

申请号：DE10162983

申请日：2001-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  FRANOSCH MARTIN

IPC: G01R1/067 ,  G01R1/073 ,  B81B1/00 ,  B81C1/00

公开(公告)号：DE10140726A1

公开(公告)日：2002-10-02

申请号：DE10140726

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEDLER HARRY ,  HUEBNER HOLGER ,  FRANOSCH MARTIN

IPC: G01R31/28 ,  H01L23/48 ,  H01L23/50 ,  H01L21/60

Abstract: Electronic component comprises: a semiconductor chip (2) having contact surfaces (4) of an integrated circuit on its active surface (3); and a bimetallic strip (5) arranged on the contact surfaces and having a fixed end (6) connected to the contact surface and a flexible free end (7) protruding from the active surface of the chip. Preferred Features: An angled bimetallic strip is arranged on the contact surfaces. The free end of the bimetallic strip has a coating made from gold or a gold alloy, or silver alloy. The bimetallic strip is made from a copper alloy and an aluminum alloy.

公开(公告)号：DE19958062C2

公开(公告)日：2002-06-06

申请号：DE19958062

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  BOECK JOSEF ,  KLEIN WOLFGANG

IPC: H01L21/331 ,  H01L29/732 ,  H01L21/8222 ,  H01L27/082

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

公开(公告)号：DE10055711A1

公开(公告)日：2002-05-23

申请号：DE10055711

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  FRANOSCH MARTIN

IPC: H01L21/3063 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a trench capacitor comprises preparing a semiconductor substrate having a number of trenches (3-9) with n-doping on its front side; applying a liquid electrolyte to the front side of the substrate; applying an electrical voltage between the rear side of the substrate and the electrolyte so that an electric current with a given current density flows in the layer and mesopores (3-30a) are produced in the trench wall; forming a first electrode in the trench and the mesopores; applying a dielectric (3-34) to the first electrode; and producing as second electrode (3-36) in the dielectric. Preferred Features: The trenches are arranged in a regular two-dimension structure and have the same shape. The surface of the substrate is covered with a horizontal electrically insulating covering layer made from a nitride in the regions between the trenches during the application of the voltage.

公开(公告)号：DE10005442A1

公开(公告)日：2001-08-16

申请号：DE10005442

申请日：2000-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHART ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: The invention relates to a bipolar transistor (20) and to a method for producing the same. The inventive bipolar transistor (20) comprises a first layer (30) disposed on a substrate (10) in which layer a collector (31) is provided, a second layer (40) disposed on the first layer (30) and provided with a base recess (41) with a base (42), and at least one further, third layer (50) disposed on the second layer (40) and provided with a feed line (51) for the base (42). Said feed line (51) is in direct contact with the base (42) in a transitional zone (52) and the third layer (50) is provided with an emitter recess (53) with an emitter. The bipolar transmitter is further provided with an undercut (43) that is disposed in the second layer (40) adjoining the base recess (41) between the first (30) and the third (50) layer, said base (42) being at least partially located also in the undercut (43). In order to obtain an as low a transition resistance as possible between the feed line (51) and the base (42), an intermediate layer (70) is provided between the first (30) and the second (40) layer, said intermediate layer (70) being selectively etchable to the second layer (40). At least in the zone of the undercut (43) between the feed line (51) and the base (42) a base connection zone (45) is provided that can be adjusted independent of other production conditions. The inventive transistor is further characterized in that the intermediate layer (70) is removed in the contact zone (46) with the base (42).

公开(公告)号：DE50214199D1

公开(公告)日：2010-03-25

申请号：DE50214199

申请日：2002-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L29/737 ,  H01L21/331