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    12.
    发明专利
    未知

    公开(公告)号：DE19631743C2

    公开(公告)日：2002-05-29

    申请号：DE19631743

    申请日：1996-08-06

    Applicant: INFINEON TECHNOLOGIES AG ,  FRAUNHOFER GES FORSCHUNG

    Inventor： GABRIC ZVONIMIR ,  SPINDLER OSWALD ,  GRASL THOMAS

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522

    Abstract: Production of an insulation layer, functioning as an inter-metal dielectric (IMD), involves: (a) covering a substrate surface (2) with a first insulating layer (3) and then a metal (preferably aluminium) layer; (b) photo-structuring the metal layer to form circuit lines (4) which are then covered with a second insulating layer (7) on their surfaces and side faces (6); (c) removing the second insulating layer material (7) from the first insulating layer regions (3) between the circuit lines (4); and (d) depositing a third insulating layer (8) on the resulting structure by ozone-activated CVD with a growth rate which is greater on the first insulating layer material (3) than on the second insulating layer material (7). Preferably, the first insulating layer material (3) is phosphosilicate glass, borophosphosilicate glass or undoped silicate glass and the second insulating layer material (7) is titanium nitride.

    14.
    发明专利
    未知

    公开(公告)号：DE10207130B4

    公开(公告)日：2007-09-27

    申请号：DE10207130

    申请日：2002-02-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEINRICH VOLKER ,  PAMLER WERNER ,  GABRIC ZVONIMIR

    IPC: H01L21/283 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

    Abstract: A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.

    15.
    发明专利
    未知

    公开(公告)号：DE10041685A1

    公开(公告)日：2002-03-21

    申请号：DE10041685

    申请日：2000-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HARTNER WALTER ,  SCHINDLER GUENTHER ,  GABRIC ZVONIMIR

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L21/8239

    Abstract: Production of a microelectronic component comprises: (i) forming a storage capacitor containing a first electrode, a second electrode and a ferroelectric or paraelectric dielectric on a substrate; and (ii) forming a barrier on the capacitor to prevent the hydrogen passing through. The hydrogen barrier is produced by forming a silicon oxide layer (41), tempering the capacitor and at least a part of the silicon oxide layer, and applying a barrier layer (42) to the tempered silicon oxide layer. Preferred Features: At least a part of the barrier layer is applied in a hydrogen-free deposition process. A first partial layer of the barrier layer is initially applied followed by a second partial layer of silicon nitride. The silicon nitride layer is deposited using a low pressure microwave process. The silicon oxide layer has partial layers (411, 412).

    16.
    发明专利
    未知

    公开(公告)号：DE19944740C2

    公开(公告)日：2001-10-25

    申请号：DE19944740

    申请日：1999-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KIRCHHOFF MARKUS ,  SPERLICH HANS-PETER ,  SCHILLING UWE ,  GABRIC ZVONIMIR ,  SPINDLER OSWALD ,  WEGE STEPHAN ,  GLAWISCHNIG HANS

    IPC: H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/314 ,  H01L21/768

    Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

    18.
    发明专利
    未知

    公开(公告)号：DE102005039323B4

    公开(公告)日：2009-09-03

    申请号：DE102005039323

    申请日：2005-08-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GABRIC ZVONIMIR ,  STICH ANDREAS ,  PAMLER WERNER ,  SCHINDLER GUENTHER

    IPC: H01L23/522 ,  H01L21/768

    Abstract: A conduction path arrangement has a substrate (1,2), at least two conduction paths (4), formed adjacent to one another over the substrate, and a cavity which is formed at least between the conduction paths (4), and a dielectric covering layer (5) covering the conduction paths and enclosing the cavity. The support paths (TB) between the substrate (1,2) and the conduction paths (4) are designed to support the conduction paths, in which on the contact surface, a width (B1) of the conduction paths is greater than a width (B2) of the support paths (TB). An independent claim is included for a method for fabrication a conduction path arrangement.

    19.
    发明专利
    未知

    公开(公告)号：DE102004050391B4

    公开(公告)日：2007-02-08

    申请号：DE102004050391

    申请日：2004-10-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN ,  TRAVING MARTIN ,  STEINLESBERGER GERNOT ,  STICH ANDREAS

    IPC: H01L21/768 ,  H05K3/00

    Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

    20.
    发明专利
    未知

    公开(公告)号：DE102004003337A1

    公开(公告)日：2005-08-18

    申请号：DE102004003337

    申请日：2004-01-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PAMLER WERNER ,  GABRIC ZVONIMIR ,  SCHINDLER GUENTHER

    IPC: C23C16/30 ,  H01L21/314 ,  H01L21/764 ,  H01L21/768 ,  C23C16/34 ,  H01L21/316

    Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

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