公开(公告)号：DE10234734A1

公开(公告)日：2004-02-12

申请号：DE10234734

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  HECHT THOMAS ,  SCHROEDER UWE ,  GOLDBACH MATTHIAS

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/22

Abstract: Method for processing a surface comprises (a) covering first sections of the surface with a metal oxide; (b) forming second sections in which the surface is exposed; and (c) modifying the surface exposed in the second sections.

公开(公告)号：DE10137830A1

公开(公告)日：2003-02-27

申请号：DE10137830

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  HECHT THOMAS ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.

公开(公告)号：DE10141084A1

公开(公告)日：2002-11-28

申请号：DE10141084

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LEONHARDT MATTHIAS

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/54

Abstract: Apparatus for depositing layers having atomic thickness on a substrate comprises a chamber with a first chamber region in which a first layer is deposited on a substrate, a second chamber region in which a second layer is deposited on the first layer and a transport system for transporting the substrate. The first and second chamber regions are separated by a chamber wall. Apparatus for depositing layers having atomic thickness on a substrate (5) comprises a chamber (10) with a first chamber region (15), into which a first process gas (20) is introduced to deposit a first layer (25) on the substrate, and a second chamber region (30), into which a second process gas (35) is introduced to deposit a second layer (40) on the first layer; and a transport system (45) to transport the substrates. A chamber wall (55) is arranged between the first chamber region and the second chamber region to separate the chamber regions. An Independent claim is also included for a process for depositing layers having atomic thickness on a substrate. Preferred Features: The chamber wall has a recess so that a substrate can pass through the chamber wall. A third chamber region (65) is arranged between the first chamber region and the second chamber region to separate the first and second chamber regions.

公开(公告)号：DE10108290A1

公开(公告)日：2002-09-12

申请号：DE10108290

申请日：2001-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GOLDBACH MATTHIAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.

公开(公告)号：DE102005024855A8

公开(公告)日：2007-03-08

申请号：DE102005024855

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  AVELLAN ALEJANDRO ,  SCHROEDER UWE ,  ORTH ANDREAS ,  GOLDBACH MATTHIAS ,  STORBECK OLAF ,  STADTMUELLER MICHAEL ,  HECHT THOMAS

IPC: H01L21/8242

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

公开(公告)号：DE50207441D1

公开(公告)日：2006-08-17

申请号：DE50207441

申请日：2002-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  HECHT THOMAS

IPC: C23C16/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The invention relates to a method for production of a metallic or metal-containing layer ( 5 ) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.

公开(公告)号：DE10321496B4

公开(公告)日：2006-07-27

申请号：DE10321496

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  BIRNER ALBERT ,  KUDELKA STEPHAN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/8242

公开(公告)号：DE102004028031A1

公开(公告)日：2006-01-05

申请号：DE102004028031

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  SCHROEDER UWE ,  HECHT THOMAS

IPC: C23C16/40 ,  H01L21/314 ,  H01L21/762 ,  H01L21/8242

Abstract: Selective coating method comprises preparing a substrate (101), covering predetermined surface regions of a substrate surface (103) with a mask, inserting a coating controlling agent (104a,104b) into the substrate in the regions of a non-covered surface of the substrate and catalytically depositing a thin layer (105) on the surface of the substrate. An independent claim is also included for: a thin layer system produced.

公开(公告)号：DE102004002242A1

公开(公告)日：2005-08-11

申请号：DE102004002242

申请日：2004-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  FOERSTER MATTHIAS ,  BIRNER ALBERT ,  ORTH ANDREAS ,  STADTMUELLER MICHAEL

IPC: H01L21/8239 ,  H01L21/334 ,  H01L21/8229 ,  H01L21/8242 ,  H01L29/94

Abstract: The invention provides a method for fabricating a memory cell, a substrate ( 101 ) being provided, a trench-type depression ( 102 ) being etched into the substrate ( 101 ), a barrier layer ( 103 ) being deposited non-conformally in the trench-type depression ( 102 ), grain elements ( 104 ) being grown on the inner areas of the trench-type depression ( 102 ), a dielectric layer ( 202 ) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements ( 104 ) growing selectively on the inner areas ( 105 ) of the trench-type depression ( 102 ) in an electrode region ( 301 ) forming a lower region of the trench-type depression ( 102 ) and an amorphous silicon layer continuing to grow in a collar region ( 302 ) forming an upper region of the trench-type depression ( 102 ).

公开(公告)号：DE10239869A1

公开(公告)日：2004-03-18

申请号：DE10239869

申请日：2002-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEGEN STEFAN ,  HECHT THOMAS ,  MOLL PETER ,  SCHROEDER UWE ,  POPP THOMAS

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L43/12 ,  H01L21/3105 ,  H01L21/31 ,  H01L21/302

Abstract: Production of dielectric layers having a high dielectric constant and low current leakage comprises preparing a substrate, forming a dielectric layer on the substrate, and subjecting the dielectric layer to a plasma.