公开(公告)号：DE10328350A1

公开(公告)日：2004-02-26

申请号：DE10328350

申请日：2003-06-24

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： COSTRINI GREG ,  HUMMEL JOHN P ,  KASKO IGOR ,  LOW KIA-SENG

IPC: H01L21/768 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

公开(公告)号：DE10131491A1

公开(公告)日：2003-01-16

申请号：DE10131491

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8239

Abstract: Production of a semiconductor storage device comprises: forming a semiconductor substrate (20), a passivating region (21) and/or a surface region (20a, 21a) with a complementary metal oxide semiconductor (CMOS) structure; forming capacitor arrangements (10-1,..., 10-4); and contacting the capacitor arrangements with the CMOS structure using contact regions or plug regions (P1, P2). At least one part of the contact regions or plug regions are formed with a region raised above the surface region of the passivating region. Preferred Features: The contact regions or plug regions are formed in a common process step, preferably after forming the passivating region.

公开(公告)号：DE10105673A1

公开(公告)日：2002-09-05

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

Abstract: Production of a stacked integrated ferroelectric semiconductor storage device or a DRAM cell comprises depositing an oxygen barrier (3) between a capacitor electrode (4) and an electrically conducting plug (1) which connects the electrode to a semiconductor electrode; and carrying out a rapid thermal processing step at 700-1000 deg C, preferably 800-900 deg C, after depositing the ferroelectric or high iota -material dielectric but before tempering. An Independent claim is also included for an integrated DRAM cell produced. Preferred Features: The temperature of the tempering step is below the temperature of the rapid thermal processing step. The oxygen barrier is made from Ir/IrOx.

公开(公告)号：DE10105997C1

公开(公告)日：2002-07-25

申请号：DE10105997

申请日：2001-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239

Abstract: Production of a ferroelectric capacitor in integrated semiconductor storage chips comprises forming an adhesion layer (3) unstructured in a region containing ferroelectric capacitors (10, 11) between a conducting plug (1a, 1b) and an oxygen barrier (4a, 4b); exposing the adhesion layer in sections by oxidizing using the oxygen barrier; and converting into an insulating layer. Preferably the adhesion layer contains tantalum. The conducting plug is made from polysilicon or tungsten. The oxidized sections extend below the edge regions of the oxygen barrier.

公开(公告)号：DE102008025473B4

公开(公告)日：2015-10-15

申请号：DE102008025473

申请日：2008-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  KASKO IGOR ,  WALTER ANDREAS

IPC: H01L45/00 ,  H01L27/24

Abstract: Verfahren zum Herstellen einer integrierten Schaltung mit einer Mehrzahl von Widerstandsänderungsspeicherzellen, wobei das Verfahren aufweist: – Ausbilden eines Halbleitersubstrats; – Ausbilden einer Isolationsschicht auf dem Halbleitersubstrat; – Ausbilden eines Grabens innerhalb der Isolationsschicht; – Einführen von Dotiermaterial eines ersten Leitungstyps durch den Graben in das Halbleitersubstrat, wodurch ein erstes Halbleitergebiet gebildet wird; – Füllen des Grabens mit einem Füllmaterial; – Ausbilden eines Kontaktloches innerhalb der Isolationsschicht benachbart zu dem Graben; – Einführen von Dotiermaterial eines zweiten Leitungstyps durch das Kontaktloch in das Halbleitersubstrat, wodurch ein zweites Halbleitergebiet gebildet wird, das zusammen mit dem ersten Halbleitergebiet eine Diode mit einem pn-Übergang ausbildet, wobei der pn-Übergang ein laterales pn-Übergangsgebiet bildet; – Entfernen des Füllmaterials; – Füllen des Grabens und des Kontaktloches mit leitendem Material, wodurch in dem Graben eine Wortleitung auf dem Halbleitersubstrat, und in dem Kontaktloch ein leitendes Verbindungselement gebildet wird; – Ausbilden eines Speicherelementes oberhalb des Halbleitersubstrats derart, dass das Speicherelement über das leitende Verbindungselement mit dem zweiten Halbleitergebiet verbunden ist.

公开(公告)号：DE19958200B4

公开(公告)日：2006-07-06

申请号：DE19958200

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NAGEL NICOLAS ,  PRIMIG ROBERT ,  KASKO IGOR ,  BRUCHHAUS RAINER

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/105

Abstract: A microelectronic structure has an adhesion layer which is disposed between a base substrate and a barrier layer. The adhesion layer improves the adhesion of the barrier layer on the base substrate, in particular to insulation layers provided there. Microelectronic structures of this type are preferably used in semiconductor memories. A method of fabricating such a microelectronic structure is also provided.

公开(公告)号：DE10355561A1

公开(公告)日：2005-06-30

申请号：DE10355561

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEZI RECAI ,  WALTER ANDREAS ,  ENGL REIMUND ,  MALTENBERGER ANNA ,  DEHM CHRISTINE ,  ARKALGUD SITARAM ,  KASKO IGOR ,  NUETZEL JOACHIM ,  KRIZ JAKOB ,  MIKOLAJICK THOMAS ,  PINNOW CARL-UWE

IPC: C09D5/24 ,  C09D5/25 ,  G11C13/02 ,  H01L27/24 ,  H01L27/28 ,  H01L51/00 ,  H01L51/30

公开(公告)号：DE10105673C2

公开(公告)日：2003-04-17

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

公开(公告)号：DE10114406A1

公开(公告)日：2002-10-02

申请号：DE10114406

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  KASKO IGOR

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L21/8247

Abstract: The invention relates to a method for producing ferroelectric memory cells in accordance with the stack principle. According to said method, an adhesive layer (2, 3) is formed between a lower capacitor electrode (6) of a memory capacitor and a conductive plug (1), which is formed below said electrode and makes an electric connection between said capacitor electrode (6) and a transistor electrode of a selection transistor that is formed in or on a semiconductor wafer. An oxygen diffusion barrier (4, 5) is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. The method is characterised by the following steps: (A) Determination of the oxygen speed of the adhesive layer (2, 3) and the diffusion coefficient (DOxygen(T)) of oxygen in the material of the adhesive layer (2, 3), dependent on the temperature (T); (B) Determination of the diffusion coefficient (DSilicon(T)) of silicon in the material of the adhesive layer (2, 3), dependent on the temperature and (C) Calculation of an optimal temperature range for the RTP step from the two diffusion coefficients, (DOxygen(T)) and (DSilicon(T)) that have been determined for a predetermined layer thickness (dBARR) and layer width (bBARR) of the layer system consisting of the adhesive layer and the oxygen diffusion barrier, so that during the RTP step the siliconisation of the adhesive layer occurs more rapidly than its oxidation.

公开(公告)号：DE10010288C1

公开(公告)日：2001-09-20

申请号：DE10010288

申请日：2000-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  KASKO IGOR ,  HARTNER WALTER ,  SCHINDLER GUENTHER

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L21/8239

Abstract: The manufacturing method has a ferroelectric layer (13) of varying thickness applied to an electrode structure (11) which has at least 2 different height levels, before application of a second electrode structure (12) to the ferroelectric layer. The different height levels are formed in the first electrode structure by formed etched edges, or by providing a step in a barrier layer (14) before deposition of the electrode structure, with a centrifugal coating process used for deposition of the ferroelectric layer.