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    11.
    发明专利
    未知

    公开(公告)号：DE59805044D1

    公开(公告)日：2002-09-05

    申请号：DE59805044

    申请日：1998-11-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

    IPC: G05F3/24 ,  H03K19/0175

    Abstract: A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.

    14.
    发明专利
    未知

    公开(公告)号：DE59801722D1

    公开(公告)日：2001-11-15

    申请号：DE59801722

    申请日：1998-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SAVIGNAC DOMINIQUE ,  FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G11C11/405 ,  G11C5/14 ,  G11C11/4074 ,  H02J9/06

    Abstract: An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.

    COLUMN REDUNDANCY DEVICE FOR A MEMORY
    15.
    发明专利
    COLUMN REDUNDANCY DEVICE FOR A MEMORY 未知

    公开(公告)号：HK1005300A1

    公开(公告)日：1998-12-31

    申请号：HK98104392

    申请日：1998-05-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SAVIGNAC DOMINIQUE ,  SOMMER DIETHER ,  WEIDENHOEFER JUERGEN

    IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C ,  G06F

    Abstract: The column redundancy device for a memory has a memory blocks (BK1... N), with memory cells arranged in x rows and y columns, redundant memory cells, which are arranged in b rows and c columns, a column decoder (CDEC) with c redundant column decoders (RCD1 ... N), and d coding elements (CF1,1 ... CFP,4). Each column decoder (RCD1 ... 4) is assigned to one of the c redundant columns of each memory block (BK1 ... N). Each of the d coding elements (CF1,1 ... CFP,4) includes means of decoding addresses, and can thus be assigned to any memory block (BK1... N).

    17.
    发明专利
    未知

    公开(公告)号：DE102005056351A1

    公开(公告)日：2006-07-13

    申请号：DE102005056351

    申请日：2005-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN

    IPC: G11C11/409 ,  G11C7/22

    Abstract: One embodiment of the present invention provides a memory device comprising a plurality of sets of memory banks, wherein each memory bank includes a memory array and is adapted to be read out in a data access; a plurality of internal data buses and a plurality of internal command and address buses connected to the plurality of sets of memory banks, respectively, such that each set of memory banks is associated with one of the internal data buses and one of the internal command and address buses; a command and address port for receiving command and address data from outside; and a command and address unit to direct the received command and address data to one of the sets of memory banks via the associated command and address bus, depending on the address data; and a data output unit for receiving data read out from one set of memory banks via the respective internal data bus in the data access and for serially outputting the received data.

    18.
    发明专利
    未知

    公开(公告)号：DE102004052612A1

    公开(公告)日：2006-05-04

    申请号：DE102004052612

    申请日：2004-10-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G11C7/10 ,  G06F11/14 ,  G11C11/4093

    Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

    19.
    发明专利
    未知

    公开(公告)号：DE102005042427A1

    公开(公告)日：2006-04-13

    申请号：DE102005042427

    申请日：2005-09-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

    IPC: G06F12/00

    Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

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