公开(公告)号：DE10104776A1

公开(公告)日：2002-08-22

申请号：DE10104776

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

Abstract: The invention relates to a method for producing a bipolar transistor having low base terminal resistance, a low defect density, and improved scalability, scalability referring to both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be maintained at a low level in the base area, as no implantations are required in order to reduce the base terminal resistance. Furthermore, the difficulties related to point defects are largely avoided.

公开(公告)号：DE59704768D1

公开(公告)日：2001-11-08

申请号：DE59704768

申请日：1997-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

IPC: C23C16/04 ,  H01L21/033 ,  H01L21/20 ,  H01L21/205 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

Abstract: The mfg. method provides a fine structure at the surface of a substrate (1,2,3) using a cathodic vapour deposition process, effected with a process gas containing SiH4 and GeH4 in a carrier gas, for providing raised areas (4) determining the size of the fine structures. The raised areas act as a mask for an etching or implantation process and have a mean dia. and mean spacing of the order of between 1 and 100nm.

公开(公告)号：DE502004007560D1

公开(公告)日：2008-08-21

申请号：DE502004007560

申请日：2004-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: H01L29/417 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

公开(公告)号：DE102006011240A1

公开(公告)日：2007-09-20

申请号：DE102006011240

申请日：2006-03-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER HERBERT ,  BOECK JOSEF ,  LACHNER RUDOLF ,  MEISTER THOMAS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/737

Abstract: A bipolar transistor has a base, an emitter and an emitter contact. The emitter has a monocrystalline layer and a polycrystalline layer, which are disposed between the base and the emitter contact in the mentioned order.

公开(公告)号：DE10231407B4

公开(公告)日：2007-01-11

申请号：DE10231407

申请日：2002-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROMANYUK ANDRIY ,  MEISTER THOMAS ,  BOECK JOSEF ,  SCHAEFER HERBERT

IPC: H01L21/28 ,  H01L29/732 ,  H01L21/331 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

公开(公告)号：DE10324081A1

公开(公告)日：2004-12-23

申请号：DE10324081

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/30 ,  G11C11/21 ,  G11C19/00 ,  H01L21/762

Abstract: The memory includes tubes (301) on the electrode layer (202) and in contact with it. A dielectric coating (302) covers them. Filler (403) intervenes in the spaces between them, and is connected to an opposite electrode (402). The configuration forms an electrical capacitor between the electrode layer and the opposite electrode, for charge storage. An independent claim is included for the method of manufacture.

公开(公告)号：DE10318422A1

公开(公告)日：2004-11-25

申请号：DE10318422

申请日：2003-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

公开(公告)号：DE10250204A1

公开(公告)日：2004-05-13

申请号：DE10250204

申请日：2002-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

公开(公告)号：DE10151203A1

公开(公告)日：2003-08-07

申请号：DE10151203

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/76

公开(公告)号：DE19953333A1

公开(公告)日：2001-05-31

申请号：DE19953333

申请日：1999-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NELLE PETER ,  SCHAEFER HERBERT ,  VIETZKE DIRK ,  STECHER MATTHIAS ,  BAUMGARTL JOHANNES ,  PERI HERMANN

IPC: H01L21/74 ,  H01L21/761 ,  H01L29/06 ,  H01L21/76

Abstract: Arrangement for realizing a trenched layer (2, 2') with a dopant comprises a counter compensation material inserted into the trenched layer, the material compensating for lattice mismatches. Preferred Features: The dopant is boron or phosphorus and germanium is the counter compensation material, or the dopant is arsenic or antimony and carbon is the counter compensation material.