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    12.
    发明专利
    未知

    公开(公告)号：DE10341059B4

    公开(公告)日：2007-05-31

    申请号：DE10341059

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  TORWESTEN HOLGER

    IPC: H01L27/08 ,  H01G9/042 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L23/522 ,  H01L27/01 ,  H01L27/06

    Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

    Multi-layer integrated circuit includes substrate with stacked circuit planes and integrates high quality passive components in its three-dimensional structure
    13.
    发明专利
    Multi-layer integrated circuit includes substrate with stacked circuit planes and integrates high quality passive components in its three-dimensional structure 未知

    公开(公告)号：DE102005045060A1

    公开(公告)日：2007-03-22

    申请号：DE102005045060

    申请日：2005-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWERD MARKUS ,  KOERNER HEINRICH ,  HOMMEL MARTINA ,  SECK MARTIN

    IPC: H01L23/522 ,  H01L21/768 ,  H01L27/08

    Abstract: The substrate (20) integrates semiconductor components. There are three circuit planes. These are designated close, intermediate or remote, with respect to the substrate, i.e. their spacing from the substrate increases with each layer. Each circuit plane contains a planar base surface and a planar covering surface adjoining a dielectric. The base surface of the circuit plane remote from the substrate (76), extends in a plane occupied by the covering surface of the intermediate circuit plane. Alternatively the base surface of the circuit plane remote from the substrate, extends in a plane lying closer to the substrate than a plane occupied by the covering surface of the intermediate circuit plane. In addition, the base surface of the intermediate circuit plane extends in a plane occupied by the covering surface of the circuit plane near the substrate. Alternatively the base surface of the intermediate circuit plane extends in a plane closer to the substrate than that occupied by the covering surface of the circuit plane close to the substrate. Circuit elements in the structure are further elaborated. A component formed by the elements (A-G), comprises one, two or more windings of a coil, a side wall of a coaxial line or parts of a condenser exceeding 10 mu m or 50 mu m in length. Salient features include use of aluminum or copper to form the tracks (34-38), at 60 atom% concentrations. They form internal conductors of the circuit (10). An even more remote conductive structure is included. One or more further circuit planes are included between the substrate and the circuit plane closest to it. An independent claim is also included for the method of manufacture.

    14.
    发明专利
    未知

    公开(公告)号：DE10327709A1

    公开(公告)日：2005-01-13

    申请号：DE10327709

    申请日：2003-06-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SECK MARTIN ,  BOETTNER THOMAS ,  HUTTNER THOMAS ,  DREXL STEFAN

    IPC: H01L21/8228 ,  H01L27/082 ,  H01L21/331

    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.

    17.
    发明专利
    未知

    公开(公告)号：DE10250204B8

    公开(公告)日：2008-09-11

    申请号：DE10250204

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

    18.
    发明专利
    未知

    公开(公告)号：DE10250204B4

    公开(公告)日：2008-04-30

    申请号：DE10250204

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

    20.
    发明专利
    未知

    公开(公告)号：DE10341059A1

    公开(公告)日：2005-04-14

    申请号：DE10341059

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  SCHWERD MARKUS ,  GOEBEL THOMAS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  TORWESTEN HOLGER

    IPC: H01L21/02 ,  H01L21/316 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08 ,  H01L21/822 ,  H01G9/042

    Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

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