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    14.
    发明专利
    未知

    公开(公告)号：DE59705303D1

    公开(公告)日：2001-12-13

    申请号：DE59705303

    申请日：1997-07-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

    IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205

    Abstract: PCT No. PCT/DE97/01408 Sec. 371 Date Feb. 9, 1999 Sec. 102(e) Date Feb. 9, 1999 PCT Filed Jul. 3, 1997 PCT Pub. No. WO98/07184 PCT Pub. Date Feb. 19, 1998For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.

    15.
    发明专利
    未知

    公开(公告)号：DE19947117A1

    公开(公告)日：2001-04-12

    申请号：DE19947117

    申请日：1999-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  REISINGER HANS ,  HANEDER THOMAS ,  BACHHOFER HARALD

    IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/22

    Abstract: According to the invention, a first source-drain region (121), a channel region (13) and a second source-drain region (122) are located in a semiconductor substrate (11). A dielectric layer (14) covers at least the surface of the channel region and parts of the first source-drain region. On the surface of said dielectric layer, a ferroelectric layer (17) is provided between two polarization electrodes (16, 18). A gate electrode is positioned on the surface of the dielectric layer. The thickness of the dielectric layer is measured in such a way that a remanent polarization of the ferroelectric layer which is aligned between the two polarization electrodes, generates compensation charges in one section of the channel region. The ferroelectric transistor is suitable for use a memory cell in a memory cell arrangement.

    16.
    发明专利
    未知

    公开(公告)号：DE502004007560D1

    公开(公告)日：2008-08-21

    申请号：DE502004007560

    申请日：2004-03-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  STENGL REINHARD ,  SCHAEFER HERBERT

    IPC: H01L29/417 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732

    Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

    18.
    发明专利
    未知

    公开(公告)号：DE10318422A1

    公开(公告)日：2004-11-25

    申请号：DE10318422

    申请日：2003-04-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732

    Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

    19.
    发明专利
    未知

    公开(公告)号：DE10250204A1

    公开(公告)日：2004-05-13

    申请号：DE10250204

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

    IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

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