公开(公告)号：DE10128211C1

公开(公告)日：2002-07-11

申请号：DE10128211

申请日：2001-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory cell (10) is embodied with a selection transistor (60) and a trench capacitor (30). The trench capacitor (30) is filled with a conducting trench filling (35), upon which an insulating cover layer (40) is arranged. A selectively grown epitaxial layer (45) is laterally grown over the insulating cover layer, starting from the substrate (15). The selection transistor (60) is embodied in the selectively grown epitaxial layer (45) and comprises a source region (65), for connection to the trench capacitor (30) and a drain region (70) for connection to a bitline. The junction depth of the source region (65) is selected such that the source region (65) extends as far as the insulating cover layer (40). In addition the thickness (50) of the epitaxial layer (45) may be optionally reduced to a suitable thickness by means of an oxidation and a subsequent etching. A contact trench (95) is then etched through the source region (65) as far as the conducting trench filling (35), which is filed with a conducting contact (90) and the conducting trench filling (35) electrically connected to the source region (65).

公开(公告)号：DE19941148A1

公开(公告)日：2001-04-19

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE102004034572B4

公开(公告)日：2008-02-28

申请号：DE102004034572

申请日：2004-07-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NOELSCHER CHRISTOPH ,  TEMMLER DIETMAR ,  MOLL PETER

IPC: G03F7/00 ,  G03F7/14 ,  H01L21/308

公开(公告)号：DE10227492B4

公开(公告)日：2006-03-09

申请号：DE10227492

申请日：2002-06-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  KRASEMANN ANKE

IPC: H01L21/8242

公开(公告)号：DE102004034572A1

公开(公告)日：2006-02-09

申请号：DE102004034572

申请日：2004-07-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NOELSCHER CHRISTOPH ,  TEMMLER DIETMAR ,  MOLL PETER

IPC: G03F7/00 ,  G03F7/14 ,  H01L21/308

公开(公告)号：DE10202140A1

公开(公告)日：2003-08-07

申请号：DE10202140

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR ,  SCHUPKE KRISTIN ,  SCHILLING UWE

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  B81C1/00

Abstract: A semiconductor component having a cavity is produced by: (i) forming a cavity in a monocrystalline silicon substrate (1), and covering walls of the cavity with a cover layer at least in an upper end region of the cavity; (ii) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (iiii) growing the covering layer only on the silicon surface. Production of a semiconductor component having a cavity comprises: (a) providing a monocrystalline silicon substrate having a silicon surface; (b) forming a cavity in the silicon substrate and covering walls of the cavity, with a cover layer at least in an upper end region of the cavity; (c) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (d) growing the covering layer only on the silicon surface to cover the cavity with the covering layer, and to form a covered cavity in the monocrystalline silicon substrate.

公开(公告)号：DE10202139A1

公开(公告)日：2003-08-07

申请号：DE10202139

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR

IPC: H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: A memory cell in a substrate (105) comprises a select transistor (160) and connected trench capacitor (110) surrounded by an second isolation layer (150). A first adjacent isolation layer (235) is thinner than the second layer but prevents lateral current flow, although the formation of a parasitic FET through cell operation is possible. An Independent claim is also included for a memory chip as above.

公开(公告)号：DE10123770A1

公开(公告)日：2002-12-05

申请号：DE10123770

申请日：2001-05-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR ,  SCHREMS MARTIN

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

Abstract: The instant invention is a method for fabricating a trench contact to a deep trench capacitor with a polysilicon filling in a trench hole formed in a silicon substrate. An epitaxy process is performed to selectively grow silicon above the polysilicon filling in the trench hole. An opening leading to the polysilicon filling is anisotropically etched into the epitaxially grown silicon. The opening has lateral dimensions that are smaller than those of the polysilicon filling, and the opening is filled with polysilicon.

公开(公告)号：DE10110974A1

公开(公告)日：2002-09-26

申请号：DE10110974

申请日：2001-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/76

公开(公告)号：DE50306393D1

公开(公告)日：2007-03-15

申请号：DE50306393

申请日：2003-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  LORENZ BARBARA ,  KOEHLER DANIEL ,  FOERSTER MATTHIAS

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/334 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.