INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION

    公开(公告)号:SG10201401254VA

    公开(公告)日:2014-11-27

    申请号:SG10201401254V

    申请日:2014-04-04

    Applicant: LAM RES CORP

    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

    PLASMA PROCESSING SYSTEMS INCLUDING SIDE COILS AND METHODS RELATED TO THE PLASMA PROCESSING SYSTEMS

    公开(公告)号:SG192846A1

    公开(公告)日:2013-09-30

    申请号:SG2013062872

    申请日:2012-02-15

    Applicant: LAM RES CORP

    Abstract: A plasma processing system for generating plasma to process a wafer. The plasma processing system includes a set of top coils for initiating the plasma, a set of side coils for affecting distribution of the plasma, and a chamber structure for containing the plasma. The chamber structure includes a chamber wall and a dielectric member. The dielectric member includes a top, a vertical wall, and a flange. The top is connected through the vertical wall to the flange, and is connected through the vertical wall and the flange to the chamber wall. The set of top coils is disposed above the top. The set of side coils surrounds the vertical wall. A vertical inner surface of the vertical wall is configured to be exposed to the plasma. The inner diameter of the vertical wall is smaller than the inner diameter of the chamber wall.

    SYSTEMS AND METHODS FOR ACHIEVING PEAK ION ENERGY ENHANCEMENT WITH A LOW ANGULAR SPREAD

    公开(公告)号:SG11202001658YA

    公开(公告)日:2020-03-30

    申请号:SG11202001658Y

    申请日:2018-08-23

    Applicant: LAM RES CORP

    Abstract: Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.

    NEAR-SUBSTRATE SUPPLEMENTAL PLASMA DENSITY GENERATION WITH LOW BIAS VOLTAGE WITHIN INDUCTIVELY COUPLED PLASMA PROCESSING CHAMBER

    公开(公告)号:SG11201906618YA

    公开(公告)日:2019-08-27

    申请号:SG11201906618Y

    申请日:2017-10-20

    Applicant: LAM RES CORP

    Abstract: WO 18/ 136 121 Al Fig. 4 Primary RF Generator Matching Circuit j — 127 100 121 71 721 71 71 771 1 7 1 7 409 Control System LU - -- ----- - -_ 102 102 103 i 103 • -I I j_4110197 11 1 - 107 X113 al 109 — 403 j — 407 Matching Matching Circuit Circuit 401 Supplemental j 405 Plasma Bias RF Density RF Generator Generato 101 123 125 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 26 July 2018 (26.07.2018) W I P 0 I PCT omit VIII °nolo VIII VIII oimIE (10) International Publication Number WO 2018/136121 Al (51) International Patent Classification: H01L 21/3065 (2006.01) HO5H 1/46 (2006.01) H01J 37/32 (2006.01) H01L 21/67 (2006.01) (21) International Application Number: PCT/US2017/057728 (22) International Filing Date: 20 October 2017 (20.10.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/408,326 17 January 2017 (17.01.2017) US (71) Applicant: LAM RESEARCH CORPORATION [US/US]; 4650 Cushing Parkway, Fremont, CA 94538 (US). (72) Inventors: TAN, Zhongkui; 4650 Cushing Parkway, Fre- mont, CA 94538 (US). ZHANG, Yiting; 4650 Cushing Parkway, Fremont, CA 94538 (US). FU, Qian; 4650 Cush- ing Parkway, Fremont, CA 94538 (US). XU, Qing; 4650 Cushing Parkway, Fremont, CA 94538 (US). WU, Ying; 4650 Cushing Parkway, Fremont, CA 94538 (US). SRIRA- MAN, Saravanapriyan; 4650 Cushing Parkway, Fremont, CA 94538 (US). PATERSON, Alex; 4650 Cushing Park- way, Fremont, CA 94538 (US). (74) Agent: WRIGHT, Kenneth, D. et al.; Martine Penilla Group, LLP, 710 Lakeway Drive, Suite 200, Sunnyvale, CA 94085 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, (54) Title: NEAR-SUBSTRATE SUPPLEMENTAL PLASMA DENSITY GENERATION WITH LOW BIAS VOLTAGE WITHIN INDUCTIVELY COUPLED PLASMA PROCESSING CHAMBER (57) : A substrate is positioned on a substrate support structure with- in a plasma processing volume of an inductively coupled plasma processing chamber. A first radiofrequency signal is supplied from a first radiofrequency signal generator to a coil disposed outside of the plasma processing volume to generate a plasma in exposure to the substrate. A second radiofrequency signal is supplied from a second radiofrequency signal generator to an electrode with- in the substrate support structure. The first and second radiofrequency signal generators are controlled independent of each other. The second radiofrequen- cy signal has a frequency greater than or equal to about 27 megaHertz. The second radiofrequency signal generates supplemental plasma density at a level of the substrate within the plasma processing volume while generating a bias voltage of less than about 200 volts at the level of the substrate. [Continued on next page] WO 2018/136121 Al IIMEDIM000101011EIEMM0M01111011H111110101111110110111111 TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))

    INTERNAL FARADAY SHIELD HAVING DISTRIBUTED CHEVRON PATTERNS AND CORRELATED POSITIONING RELATIVE TO EXTERNAL INNER AND OUTER TCP COIL

    公开(公告)号:SG10201603087TA

    公开(公告)日:2016-05-30

    申请号:SG10201603087T

    申请日:2012-04-24

    Applicant: LAM RES CORP

    Abstract: Plasma processing chambers having internal Faraday shields with defined groove configurations, are defined. In one example, the chamber includes an electrostatic chuck for receiving a substrate and a dielectric window connected to a top portion of the chamber, where the dielectric window disposed over the electrostatic chuck. Also included is a Faraday shield disposed inside of the chamber and defined between the electrostatic chuck and the dielectric window. The Faraday shield includes an inner zone having an inner radius range, a middle zone having a middle radius range, an outer zone having an outer radius range, where the inner zone is adjacent to the middle zone, and the middle zone being adjacent to the outer zone. Further defining the Faraday shield is a first set of radial slots (A) extending through the inner zone, the middle zone, and the outer zone, a second set of radial slots (C) extending through only the outer zone; and a third set of radial slots (B) extending through the middle zone and outer zone. In this configuration, the first, second and third radial slots are arranged radially around the Faraday shield in a repeating pattern of slots A, C, B, and C.

    INTERNAL FARADAY SHIELD HAVING DISTRIBUTED CHEVRON PATTERNS AND CORRELATED POSITIONING RELATIVE TO EXTERNAL INNER AND OUTER TCP COIL

    公开(公告)号:SG194224A1

    公开(公告)日:2013-11-29

    申请号:SG2013078704

    申请日:2012-04-24

    Applicant: LAM RES CORP

    Abstract: Plasma processing chambers having internal Faraday shields with defined groove configurations, are defined. In one example, the chamber includes an electrostatic chuck for receiving a substrate and a dielectric window disposed over the electrostatic chuck. Also included is a Faraday shield inside of the chamber and between the electrostatic chuck and the dielectric window. The Faraday shield includes an inner zone, a middle zone adjacent to the inner zone, and an outer zone adjacent to the middle zone. Further defining the Faraday shield is a first set of radial slots (A) extending through all three zones, a second set of radial slots (C) extending through only the outer zone; and a third set of radial slots (B) extending through the middle and outer zones. The first, second and third radial slots are arranged radially around the Faraday shield in a pattern of slots A, C, B, and C.

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