CMOS GATE STRUCTURE
    11.
    发明专利

    公开(公告)号:JPH11289017A

    公开(公告)日:1999-10-19

    申请号:JP33315098

    申请日:1998-11-24

    Abstract: PROBLEM TO BE SOLVED: To obtain a CMOS gate structure in which a dopant does not creep at all treatment temperatures, by a method wherein a silicide which is annealed and treated is formed of large particle-size polysilicon of a lower multilayer structure. SOLUTION: After a polysilicon multilayer structure 20 is formed, a silicide layer 22 (WSix ) is deposited. The silicide layer 20 has a thickness of 50 Åor lower. After that, the silicide layer 22 is annealed and treated in an NH3 atmosphere, and the silicide layer 22 is nitrided. The silicide layer 22 functions as an intermediate dopant barrier layer in a final gate stack structure. After that, the second bulk deposition of the silicide layer 22 is performed, and a silicide layer 24 is deposited on the silicide layer 22 which has become the barrier layer. After that, a final annealing treatment is performed, the silicide layer 22 and the silicide layer 24 form a structure similar to the structure of the particle size of the polysilicon multilayer structure 20. Since the particle size is uniform, a dopant does not creep to the structure 20 irrespective of a treatment temperature.

    MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT

    公开(公告)号:JP2000216191A

    公开(公告)日:2000-08-04

    申请号:JP2000007951

    申请日:2000-01-17

    Abstract: PROBLEM TO BE SOLVED: To form a barrier layer on a copper, to form an aluminum pad on the barrier, and then to bond a gold wire to a copper metallized layer on the aluminum pad. SOLUTION: A cap layer 72 is formed on a silicon board 11, and a window is provided to expose a copper metallized layer in the cap layer 72. The barrier 73 and an aluminum layer 74 are blanket-deposited on the cap layer 72 and also in the window to come into contact with the copper metallized layer. Thereafter, the aluminum layer 74 is masked with a mask 76, the aluminum layer 74 and the barrier layer 73 are etched to form an aluminum bonding pad 77, the mask 76 is removed off, and a gold wire is bonded by thermocompression. By this setup, a gold wire can be bonded to a copper metallized layer.

    INTEGRATED CIRCUIT DEVICE PROVIDED WITH DUAL DAMASCENE CAPACITOR AND RELATED METHOD FOR MANUFACTURE

    公开(公告)号:JP2000208743A

    公开(公告)日:2000-07-28

    申请号:JP2000006223

    申请日:2000-01-12

    Abstract: PROBLEM TO BE SOLVED: To provide a high dielectric constant and quality with less insulation leakage so that reduction of an insulating layer by the metal of an electrode is prevented, by allowing a capacitor to comprise a substantially flat upper side surface, so formed as to be substantially the same plane as adjoining upper side surface part of an insulating layer. SOLUTION: An electrolytic capacitor 24 comprises a substantially flat upper side surface, so formed as to be substantially the same plane with the upper side surface part of an adjoining third insulating (dielectric) layer 42. The end of a lower side metal electrode 44 and that of a capacitor insulating (dielectric) layer 46 are terminated at the upper side surface of a capacitor. The capacitor insulating layer 46 has a permittivity almost equal to 25 or above which attains a desired capacitor characteristics. An upper side electrode comprises a conductive metal layer 48 and a conductive metal layer 50. The conductive metal layer 48 functions as a barrier layer as well, preventing a metal from the metal conductive layer 50, for example, copper from diffusing in the insulating layer 46.

    CAPACITY OF INTEGRATED CIRCUIT INCLUDING FIXED PLUG

    公开(公告)号:JP2000208731A

    公开(公告)日:2000-07-28

    申请号:JP2000004300

    申请日:2000-01-13

    Abstract: PROBLEM TO BE SOLVED: To provide a capacity of an integrated circuit including a fixed plug. SOLUTION: The capacity of an integrated circuit contains a substrate, a first dielectric substance layer 26 which is adjacent to the substrate and is provided with a first groove in the substrate, and a first metal plug 30 extending upward in the first groove 28. A mutual connection line 32 lies on the first groove 28 and is in contact with the first metal plug 30 for specifying a fixed recessed part on the opposite side to the first metal plug 30. A second dielectric substance layer 36 lies on the mutual connection line 32 and is provided with a second groove 38 therein. The second metal plug 22 extends upwards in the second groove 38. More specifically, the second metal plug 22 includes a base body extending upwards in the second groove 38 and a fixing part, which is connected with the base body and of which fixing recessed part allows the second metal plug 32 to be fixed to the mutual connection line 32. The second groove 38 can be made deep for fixing the second metal plug 22, without loosening the metal plug and separation thereof from the lower mutual connection line.

    BONDING OF ALUMINUM OXIDE COMPONENT TO SILICON SUBSTRATE

    公开(公告)号:JPH11109183A

    公开(公告)日:1999-04-23

    申请号:JP20614198

    申请日:1998-07-22

    Abstract: PROBLEM TO BE SOLVED: To enable the bonding excellent in reliability of a component to a substrate by forming a layer containing a metal such as titanium on a substrate including cavities, forming a layer containing aluminum on the titanium layer, and bonding an oxide component to the aluminum layer to improve the adhesion to aluminum. SOLUTION: A first layer 36 containing aluminum is formed on a part of a substrate including cavities. An oxide component 16 is bonded to the aluminum layer 36. A second layer 35 containing one material selected from a group comprising titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum and tungsten, is formed on a part of the substrate 11 including cavities, and the aluminum layer 36 is formed on a second layer 35.

    SEMICONDUCTOR DEVICE
    16.
    发明专利

    公开(公告)号:JPH10270552A

    公开(公告)日:1998-10-09

    申请号:JP6345098

    申请日:1998-03-13

    Abstract: PROBLEM TO BE SOLVED: To provide the method for forming a conducting layer for connecting an opening that is not oxidized during the manufacturing process, and the semiconductor device having the conducting layer such as this. SOLUTION: This semiconductor device comprises a substrate having a concave part, a readily oxidizable conducting layer 20 which fills at least a part of the concave part for forming a plug in the above described concave part and is formed at least on a part of the substrate, and a protecting layer 22 made of metal, which is at least partially diffused into the conducting layer 20. The protecting layer 22 made of metal has the higher affinity for oxygen than the conducting layer 20 and absorbs the oxygen during the reflow process of the conducting layer 20.

    CAPACITOR FOR INTEGRATED CIRCUIT
    18.
    发明专利

    公开(公告)号:JP2000294746A

    公开(公告)日:2000-10-20

    申请号:JP2000004788

    申请日:2000-01-13

    Abstract: PROBLEM TO BE SOLVED: To obtain a compact capacitor that solves a problem regarding a leakage current or other problems. SOLUTION: The capacitor for an integrated circuit is composed of a conductive plug 7 with an upper surface and an exposed sidewall, and an electrode layer 9 formed on the sidewall of the conductive plug 7. Then, the above side wall includes a layer 3 or 5 made of a material selected form a group consisting of titanium(Ti) and titanium nitride(TiN), and the material of the electrode layer 8 contains neither titanium(Ti) not the titanium nitride(TiN).

    INTEGRATED CIRCUIT CAPACITOR AND RELATED MANUFACTURE

    公开(公告)号:JP2000208732A

    公开(公告)日:2000-07-28

    申请号:JP2000006226

    申请日:2000-01-12

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit capacitor provided with metallic electrodes and is improved in reliability by arranging a capacitor dielectric layer on a lower metallic electrode and an upper metallic electrode on the dielectric layer. SOLUTION: An integrated circuit capacitor 20 is formed on a substrate 24 and a dielectric layer 28 is formed on an interconnecting line 26 laid adjacently to the substrate 24. A metallic plug 32 is arranged in the dielectric layer 28. The capacitor 20 contains lower and upper multilayered metallic electrodes 36 and 40 and a capacitor dielectric layer 38 formed between the electrodes 36 and 40. The lower electrode 36 is in contact with the plug 32. A second dielectric layer, namely, the capacitor dielectric layer 38 lies on the lower electrode 36 and the upper electrode 40 lies on the second dielectric layer. The dielectric layer 38 lies on the lower electrode 36 and is composed of, for example, silicon dioxide, silicon nitride, and/or a material having an appropriate large dielectric constant, or the alloy of the material.

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