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    PROCEDE DE FORMATION D'UNE PORTION MONOCRISTALLINE A BASE DE SILICIUM
    11.
    发明专利
    PROCEDE DE FORMATION D'UNE PORTION MONOCRISTALLINE A BASE DE SILICIUM 未知

    公开(公告)号：FR2900277A1

    公开(公告)日：2007-10-26

    申请号：FR0603453

    申请日：2006-04-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  RUBALDO LAURENT ,  TALBOT ALEXANDRE

    IPC: H01L21/306

    Abstract: Des portions monocristallines (2) à base de silicium sont réalisées sur une surface (S) d'un substrat (100), sélectivement dans des zones (101) où un matériau monocristallin est initialement découvert. Pour cela, une couche (1) est d'abord formée sur toute la surface du substrat, en utilisant un précurseur de silicium du type hydrure non-chloré, et dans des conditions adaptées de sorte que la couche est monocristalline dans les zones du substrat où un matériau monocristallin est initialement découvert, et amorphe en dehors de ces zones. Les portions amorphes de la couche (1) sont ensuite sélectivement gravées, de sorte que seules les portions monocristallines (2) de la couche restent sur le substrat.

    FORMATION D'UNE PORTION DE COUCHE SEMICONDUCTRICE MONOCRISTALLINE SEPAREE D'UN SUBSTRAT
    12.
    发明专利
    FORMATION D'UNE PORTION DE COUCHE SEMICONDUCTRICE MONOCRISTALLINE SEPAREE D'UN SUBSTRAT 未知

    公开(公告)号：FR2897471A1

    公开(公告)日：2007-08-17

    申请号：FR0650474

    申请日：2006-02-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

    IPC: H01L21/20 ,  H01L21/336

    Abstract: L'invention concerne un procédé de formation d'une portion de couche semiconductrice monocristalline (40) au dessus d'une zone évidée, comprenant les étapes consistant à faire croître par épitaxie sélective sur une région active semiconductrice monocristalline (32) une couche semiconductrice monocristalline sacrificielle (38) et une couche semiconductrice monocristalline (40), et éliminer la couche sacrificielle (38). La croissance épitaxiale est réalisée alors que la région active est entourée d'une couche isolante en surépaisseur (34) et l'élimination de la couche semiconductrice monocristalline sacrificielle (38) est effectuée par un accès résultant d'une élimination au moins partielle de la couche isolante en surépaisseur.

    15.
    发明专利
    未知

    公开(公告)号：FR2779572A1

    公开(公告)日：1999-12-10

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

    19.
    发明专利
    未知

    公开(公告)号：DE60314203D1

    公开(公告)日：2007-07-19

    申请号：DE60314203

    申请日：2003-04-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： MONFRAY STEPHANE ,  DUTARTRE DIDIER ,  BOEUF FREDERIC

    IPC: H01S5/34 ,  H04L9/08

    Abstract: An integrated circuit, incorporating a semiconductor device forming the source of a single photon, comprises on a silicon substrate (SB): (a) a MOS transistor (TR) having a grid in the shape of a mushroom, capable of delivering on its drain, in a controlled manner, a single electron in response to a control voltage applied on its grid; (b) at least one compatible silicon quantum box (BQ), electrically coupled to the drain region (D) of the transistor, and capable of emitting a single photon on the reception of a single electron emitted by the transistor. Independent claims are also included for: (a) a cryptographic device incorporating this integrated circuit; (b) a method for the fabrication of this integrated circuit; (c) a method for the emission of a single photon using this integrated circuit.

    20.
    发明专利
    未知

    公开(公告)号：FR2812764B1

    公开(公告)日：2003-01-24

    申请号：FR0010176

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

    IPC: H01L21/762 ,  H01L21/328

    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

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