中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.023 seconds)

    11.
    发明专利
    未知

    公开(公告)号：DE69431656D1

    公开(公告)日：2002-12-12

    申请号：DE69431656

    申请日：1994-08-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRIANTI FRANCESCO ,  ALINI ROBERTO ,  PISATI VALERIO ,  GADDUCCI PAOLO

    IPC: H03H11/04 ,  H03H1/00

    Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (iK1, iK2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

    12.
    发明专利
    未知

    公开(公告)号：IT1309712B1

    公开(公告)日：2002-01-30

    申请号：ITMI990350

    申请日：1999-02-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  MARCHESE STEFANO ,  SAVO ALESSANDRO

    IPC: H03G1/00

    Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

    13.
    发明专利
    未知

    公开(公告)号：DE69614248D1

    公开(公告)日：2001-09-06

    申请号：DE69614248

    申请日：1996-05-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  COSENTINO GAETANO ,  VAI GIANFRANCO

    IPC: H03F3/45 ,  H03F3/72 ,  H03H1/00

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    14.
    发明专利
    未知

    公开(公告)号：DE69901781D1

    公开(公告)日：2002-07-18

    申请号：DE69901781

    申请日：1999-03-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO ,  MARCHESE STEFANO

    IPC: H03G1/00

    Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

    16.
    发明专利
    未知

    公开(公告)号：DE69614501T2

    公开(公告)日：2002-04-11

    申请号：DE69614501

    申请日：1996-03-08

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PISATI VALERIO

    IPC: H03L7/099 ,  H03B1/00

    Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

    19.
    发明专利
    未知

    公开(公告)号：DE69520562T2

    公开(公告)日：2001-07-12

    申请号：DE69520562

    申请日：1995-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

    IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

    Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

    20.
    发明专利
    未知

    公开(公告)号：ITMI20000393D0

    公开(公告)日：2000-02-29

    申请号：ITMI20000393

    申请日：2000-02-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASTELLO RINALDO ,  PORTALURI SALVATORE ,  PISATI VALERIO ,  CAZZANIGA MARCO

    IPC: H03F1/42 ,  H03H11/04

    Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

Patent Agency Ranking