公开(公告)号：US20210151561A1

公开(公告)日：2021-05-20

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Xiaohong CHENG ,  Qingzhu ZHANG ,  Huaxiang YIN ,  Wenwu WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US20210125873A1

公开(公告)日：2021-04-29

申请号：US16924057

申请日：2020-07-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Hong YANG ,  Xiahong CHENG ,  Xiaolei WANG ,  Xueli MA ,  Wenwu WANG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/165 ,  H01L29/51 ,  H01L21/02

Abstract: The disclosure provides a method for fabricating a semiconductor device, in which a core device of the semiconductor device employs a stacked nanowires or nanosheets structure, and an input/output device of the semiconductor device employs FinFET structure. The disclosure also provides a FinFET with an input/output device compatible with the stacked nanowires or nanosheets. The solution of the disclosure solves the problem that if the input/output device employs stacked nanowires or nanosheets device, it is difficult to fill a metal gate between two nanowires or nanosheets due to the thicker dielectric layer, and even if the metal gate is filled partially, the electrical performance of the input/output device is still poor.

公开(公告)号：US10991877B2

公开(公告)日：2021-04-27

申请号：US16560357

申请日：2019-09-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Meiyin Yang ,  Jun Luo ,  Sumei Wang ,  Jing Xu ,  Yanru Li ,  Junfeng Li ,  Yan Cui ,  Wenwu Wang ,  Tianchun Ye

IPC: H01L43/12 ,  H01F41/32 ,  H01F10/32 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  G11C11/56 ,  H01L27/22

Abstract: A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.

公开(公告)号：US20210074334A1

公开(公告)日：2021-03-11

申请号：US16957468

申请日：2018-09-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: G11C5/06 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/06 ,  H01L29/78 ,  G11C16/24 ,  G11C16/08

Abstract: A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.

公开(公告)号：US20210043762A1

公开(公告)日：2021-02-11

申请号：US16966862

申请日：2018-10-31

Applicant: Institute of Microelectronics, The Chinese Academy of Sciences

Inventor： Huilong ZHU

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same. According to an embodiment, the semiconductor device may include a vertical active region disposed on a substrate and comprising a first source/drain layer, a channel layer and a second source/drain layer which are stacked in sequence; a gate stack surrounding at least a part of a periphery of the channel layer; and at least one of: a first electrical connection component for the first source/drain layer, comprising a first contact portion disposed above a top surface of the active region and a first conductive channel in contact with the first contact portion and extending from the top surface of the active region to be in contact with at least a part of sidewalls of the first source/drain layer; and a second electrical connection component for the gate stack, comprising a second contact portion disposed above the top surface of the active region and a second conductive channel in contact with the second contact portion and extending from the top surface of the active region to be in contact with at least a part of sidewalls of a gate conductor layer in the gate stack.

公开(公告)号：US20210043761A1

公开(公告)日：2021-02-11

申请号：US16868708

申请日：2020-05-07

Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES

Inventor： Sen HUANG ,  Xinhua WANG ,  Ke WEI ,  Xinyu LIU ,  Wen SHI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  G01N27/414

Abstract: A detector based on a gallium nitride-based enhancement-mode device and a manufacturing method thereof. The detector is a gas or solution detector. When the detector is used in electrolyte solution detection, electrolyte solution is located in the gate opening region and directly contacts the thin barrier layer to form a contact interface. The electrolyte solution affects interface charges at the contact interface, leading to a change in a concentration of the two-dimensional electron gas, and further a change in a current between the source and the drain. When the detector is used in a hydrogen-containing gas detection, the H concentration of the hydrogen-containing gas affects interface charges at the contact interface between the gate and the thin barrier layer, leading to a change in a concentration of the two-dimensional electron gas, and further a change in the current between the source and the drain.

公开(公告)号：US10892564B1

公开(公告)日：2021-01-12

申请号：US16885717

申请日：2020-05-28

Applicant: ETHETA COMMUNICATION TECHNOLOGY (SHENZHEN) CO.,LTD ,  EAST CHINA RESEARCH INSTITUTE OF MICROELECTRONICS

Inventor： Huan-Chu Huang ,  Junyong Liu ,  Hong Lin ,  Hao Sun ,  Zhixing Qi ,  Minhui Zeng ,  Yanchao Zhou ,  Jingwei Li ,  Tao Ma

IPC: H01Q1/24 ,  H01Q21/28 ,  H01Q21/06 ,  H01Q9/04 ,  H01Q21/08

Abstract: The present invention discloses an integration module of millimeter-wave and non-millimeter-wave antennas, comprising a module carrier, one or more millimeter-wave antennas, one or more non-millimeter-wave antennas, and a radio frequency integrated circuit; the radio frequency integrated circuit is electrically connected to the millimeter-wave antenna(s); the radio frequency integrated circuit and the non-millimeter-wave antenna(s) are set in the same plane as or a space non-parallel with that of the module carrier. With the present invention, the height space on the side of a mobile communication device can be fully used, so that it is not necessary to occupy a large amount of horizontal area, thereby reducing the requirements of the antenna module for the overall size of the mobile communication device, and thus reducing cost and enhancing product competitiveness.

公开(公告)号：US10833193B2

公开(公告)日：2020-11-10

申请号：US15720913

申请日：2017-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/223 ,  H01L27/092

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

公开(公告)号：US10825738B2

公开(公告)日：2020-11-03

申请号：US16222570

申请日：2018-12-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

公开(公告)号：US20200335165A1

公开(公告)日：2020-10-22

申请号：US16959225

申请日：2018-01-22

Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES

Inventor： Qi LIU ,  Wei WANG ,  Sen LIU ,  Feng ZHANG ,  Hangbing LV ,  Shibing LONG ,  Ming LIU

IPC: G11C13/00 ,  H03K19/20

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.