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公开(公告)号：JPH0833323A
公开(公告)日：1996-02-02
申请号：JP32147194
申请日：1994-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： ROSSI DOMENICO , TANAKA KAZUYUKI
Abstract: PURPOSE: To provide a boost converter which suitably drives the capacitive load direct and is easily miniaturized with a simple circuit. CONSTITUTION: One terminal of an inductor L, which is connected to a supply rail VDD through a 1st switch SWA, is connected to an output node VOUT to which a capacitive load C is connected through a 1st discharge path (SWC+D1) and the other terminal of the inductor, which is grounded through a 2nd switch SWB is connected to the output node through a 2nd discharge path (SWD+D2).
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公开(公告)号：JPH07298301A
公开(公告)日：1995-11-10
申请号：JP10261595
申请日：1995-04-26
Applicant: CONS RIC MICROELETTRONICA , ST MICROELECTRONICS SRL
Inventor： MANCUSO MASSIMO , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PURPOSE: To provide high resolution of video and to eliminate the defects of conventional techniques by providing a calculation block which is connected to an input terminal and operated by a fuzzy-logic based processing method and which executes a switch between at least two different interpolation processing methods. CONSTITUTION: For a TV signal scanning converting device 1, luminance/ chrominance signals CFy and CFuv and signals PFy and PFuv corresponding to image fields are inputted to an interface(IF) 2. The IF 2 is operated with a fuzzy logic and supplies TV signals components Xy and Piy to input terminals Pi and X of a filtering block 3. A calculation block CALC1 is operated with a fuzzy logic processing method, receives a luminance component Y and detects the front and motion of a TV signal, while utilizing information in two continuous image fields. On the other hand, an arithmetic block 5 inputs an average parameter, which is calculated based on pixels (Pi , Pj and x) of image fields, to the calculation block CALC1 . A block MAX calculates and outputs the peak value of plural signals to be inputted.
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公开(公告)号：JPH07260838A
公开(公告)日：1995-10-13
申请号：JP31904394
申请日：1994-11-29
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PALARA SERGIO , SUERI STEFANO
IPC: G01R31/26 , F02P3/05 , G01R19/165 , H03K17/08 , H03K17/64
Abstract: PURPOSE: To generate a diagnostic signal indicating reach of current flowing through a power transistor in a presetting level by driving the first circuit, in which maximum current is restricted by a single signal serving as a function of the voltage difference, and a threshold circuit generating the diagnostic signal. CONSTITUTION: A comparator is constructed of a differential amplifier A which can generate a signal as a function of the difference between a reverence voltage E1 and a voltage in a sensing resistor RS, through which current IC flowing in a power transistor T1 (and a load L) flows. The signal generated by the comparator A drives two circuits. The first circuit (LIMITATOR) generates a restriction signal for the maximum current flowing in the transistor T1 and works on a driving circuit (DRIVE) transmitting driving current to the transistor T1 . The second circuit (DIAGNOSTIC) is set by the first circuit and generates a diagnostic signal VD, after the current IC reaches a value smaller than the limit value for the current IC by the previously set value.
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公开(公告)号：JPH07212156A
公开(公告)日：1995-08-11
申请号：JP23539794
申请日：1994-09-29
Applicant: ST MICROELECTRONICS SRL
Inventor： ROSSI GIORGIO , MARCHIO FABIO , LUONI LIANA , COCETTA FRANCO
IPC: H03G11/00 , H03F1/52 , H03G11/02 , H03K17/082
Abstract: PURPOSE: To decrease a voltage across an equalization capacitor, to accelerate a charging process, and to make a current limiting action proper by providing an uni-directional current energizing circuit between one terminal the equalization capacitor and the gate of a power MOS transistor. CONSTITUTION: When a voltage across a resistor Rs is increased, and allowed to reach the voltage of a reference power source Vr, a transistor TRQ5 is turned off. Then, a TrQ4 turns on a TrQ6 to draw more current from the base of the TrQ6. Some portion of current Ig is thus allowed to flow to the emitter of the TrQ6, the gate voltage of a power MOSTrMp is decreased, and load current I is decreased. At this time, a equalization capacitor C is not sufficiently charged, and the TrQ4 draws current from the base of the TrQ6, and the gate of the TrMp continues to draw current from a current source Ig while the TrQ6 is turned off, and increases the load current I. When an unidirectional current energizing circuit 2 is arranged at a prescribed position, the equalization capacitor C can be charged at a higher rate. Also, an amplifier 1 is properly interposed, and the current I is limited at an output terminal F.
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公开(公告)号：JPH07200339A
公开(公告)日：1995-08-04
申请号：JP29700494
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , OLIVO MARCO
IPC: G01R31/28 , G01R31/3185 , G06F7/00 , G06F11/22 , G11C29/48
Abstract: PURPOSE: To provide a circuit constitution and its method which can facilitate a PLA(programmable logic array) test with higher safety and at a higher speed. CONSTITUTION: A circuit constitution 1 which tests a matrix 2 is provided with a series of input latches 7 and output latches 8 which are connected to the matrix 2, and at least a test data bus 11 and a test address bus 12 which are connected to the latches 7 and 8. In such a constitution, the matrix test time is considerably shortened.
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Patent Agency Ranking
公开(公告)号：JPH07176138A
公开(公告)日：1995-07-14
申请号：JP25471694
申请日：1994-09-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , BETTI GIORGIO , ALINI ROBERTO
Abstract: PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a first RC1 and synthesizing the signals in a second RC2. CONSTITUTION: The first RC1 processes the Q output tap (6:0) value of an FF for forming the shift register SR prior to the processing by the second RC2 of the corresponding bit for the complete two cycles of a synchronous block signal VCO. In order to secure the utilization of the entire cycle of the clock signal VCO which is a corresponding decoding value ND1 in the input D of the output register (FF) of a decoding NRZ output stream, a frequency which is partial compared to the base synchronous clock signal VCO in front of the rising front of a first clock signal and matched with the bit number ratio of input and output streams is provided. The bit finally processed in the RC2 is tentatively stored in the shift registers Q1-Q7, the time when the (n) bits are processed in the RC1 is predicted and the signals are synthesized in the RC2.
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公开(公告)号：JPH07176004A
公开(公告)日：1995-07-14
申请号：JP40507490
申请日：1990-12-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MURARI BRUNO , ROSSI DOMENICO , SAVINO PIERANTONIO
Abstract: PURPOSE: To provide a preamplifier capable of being directly connected to a magnetic head and eliminating the need of the presence of especially a reference voltage source different from a power supply voltage or the capacitor having a high value. CONSTITUTION: Differential circuits T5 and T6 provided with an input stage provided with the differential circuit and a transistor output stage T2 are provided. A differential stage is provided with an intrinsic offset voltage and can be grounded and directly connected to the magnetic head L. Transistors T5 and T6 form the differential circuit provided with a different bias current so as to reduce input equivalent noise. The magnetic head L is connected to the base terminal of the transistor T5 and the base terminal of the transistor T6 is connected to the intermediate point of a pair of resistors R1 and R2 serially connected with each other between the output stage T2 and the line of a reference voltage. In the form, the differential stages T5 and T6 bias output by the offset voltage without the need of additional components for the purpose.
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公开(公告)号：JPH07152569A
公开(公告)日：1995-06-16
申请号：JP17690794
申请日：1994-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor： PAGNI ANDREA , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PURPOSE: To greatly reduce a storage area for storing belonging relation functions from the IF portion of a fuzzy rule and the calculation operation of a THEN portion by providing a conversion block in an input part and providing at least one memory block for storing information relating to the IF conditions of an IF-THEN rule set in the conversion block. CONSTITUTION: The conversion block 5 for forming this input part of an electronic controller operated in a fuzzy logic form is provided with the memory block 6 and the memory block 6 stores data relating to the belonging relation functions relating to the IF portion of the fuzzy rule. The memory block 6 is divided into an imaging area 7 and an activating area 8. The imaging area 7 is provided with the set of the belonging relation functions relating only to the IF conditions in the IF-THEN rule set and the activating area 8 is provided with the data for relating the respective logic variables of a fuzzy type relating to a control process to the corresponding ones of the belonging relating functions in the set.
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公开(公告)号：JPH07147646A
公开(公告)日：1995-06-06
申请号：JP12279994
申请日：1994-06-03
Applicant: ST MICROELECTRONICS SRL
Inventor： D ALTO VIVIANA , AIROLDI FABRIZIO , SCALISE FABIO , PODESTA MARIA GRAZIA
Abstract: PURPOSE: To suppress video signal echoes in a television equalizer. CONSTITUTION: A first digital filter 2 in television equalizer 1 supplies an output upon receiving a video signal x(k) and a first adding node 3 in the equalizer 1 supplies an equalizer output signal y(k) upon receiving the output of the filter 2. A digital filter 5 in the equalizer 1 supplies an output to the node 3 upon receiving the equalizer output signal y(k) and a second adding node in the equalizer 1 supplies an error signal e(k) which is equal to the difference between the equalizer output signal y(k) and a reference signal d(k). An echo suppressing circuit 4 supplies a filter coefficient updated upon receiving the error signal e(k) to the first and second digital filters 2 and 5.
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公开(公告)号：JPH07115355A
公开(公告)日：1995-05-02
申请号：JP24706894
申请日：1994-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , GADDUCCI PAOLO , MOLONEY DAVID
IPC: H03F1/30 , H03F3/45 , H03K5/1536 , H03K17/13 , H03K17/60
Abstract: PURPOSE: To eliminate the equivalent input offset of a comparator stage by cyclically inverting the connection of the input terminal of a comparator for supplying input signals after a detected zero cross. CONSTITUTION: After detecting that the zero cross is generated, comparison is performed with a minimum interval between the optional continuous two times of the zero crosses of the input signals S1 and an output state taken by the comparator G1 for practically small preliminarily set time is stored. This circuit is realized by using a deviater D for switching the input connection of the comparator G1 for supplying output signals S2 to the clock input terminal CK of a flip-flop for storing the output state. The flip-flop is sensitive to the unidirectional transition of clock signals S2 and the deviater D is driven by signals S7 delayed for a preliminarily set time interval by a delay circuit.
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