公开(公告)号：KR101865626B1

公开(公告)日：2018-06-11

申请号：KR1020110116174

申请日：2011-11-09

Applicant: 삼성전자주식회사

Inventor： 강종훈 ,  구봉진 ,  김태곤 ,  최한메 ,  김기철 ,  조은영

IPC: H01L21/20

CPC classification number: H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/268 ,  H01L21/324 ,  H01L29/045

Abstract: 박막구조물및 그제조방법에서, 박막구조물은기판상에형성된블록킹패턴과, 상기블록킹패턴사이의기판상에구비되고노출되는면이모두 (100) 면인단결정반도체막을포함한다. 상기박막구조물에포함된단결정반도체막은깍여진측면부없이균일한결정성을갖는다.

公开(公告)号：KR1020130051051A

公开(公告)日：2013-05-20

申请号：KR1020110116174

申请日：2011-11-09

Applicant: 삼성전자주식회사

Inventor： 강종훈 ,  구봉진 ,  김태곤 ,  최한메 ,  김기철 ,  조은영

IPC: H01L21/20

CPC classification number: H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/268 ,  H01L21/324 ,  H01L29/045

Abstract: PURPOSE: A thin film structure and a forming method thereof are provided to obtain a high electrical property by including a single crystal semiconductor layer with uniform crystallinity. CONSTITUTION: Blocking patterns(104) are formed on a substrate and suppresses the growth of a single crystal semiconductor layer(106). The single crystal semiconductor layer is formed on the substrate between the blocking patterns. The single crystal semiconductor layer is formed with a selective epitaxial growing process and is formed in a gap between the blocking patterns.

Abstract translation: 目的：通过包括具有均匀结晶度的单晶半导体层，提供薄膜结构及其形成方法以获得高电性能。 构成：在衬底上形成阻挡图案（104）并抑制单晶半导体层（106）的生长。 单晶半导体层在阻挡图案之间的基板上形成。 单晶半导体层由选择性外延生长工艺形成，并形成在阻挡图案之间的间隙中。

公开(公告)号：KR1020120119781A

公开(公告)日：2012-10-31

申请号：KR1020110037964

申请日：2011-04-22

Applicant: 삼성전자주식회사

Inventor： 강곤수 ,  강상범 ,  박재영 ,  강성호 ,  김태곤 ,  엄현섭 ,  강종훈 ,  문강훈 ,  이한기

IPC: H01L21/683

CPC classification number: F27B17/0025 ,  H01L21/67115 ,  H01L21/6875

Abstract: PURPOSE: A support unit and a substrate processing apparatus having the same are provided to minimize damage to the substrate in a thermal process about the substrate. CONSTITUTION: A processing space processing a substrate is supplied inside a chamber(100). A support unit(1000) supports the substrate. A heating member(200) heats the substrate. A plurality of support pins(1040) is upwardly protruded from a plate. At least one sub pin(1060) is projected from the plate to the top. The support pin is located around the sub pin. [Reference numerals] (226) Power supply unit; (248) Power supply unit; (300) Controller

Abstract translation: 目的：提供一种支撑单元和具有该支撑单元的基板处理装置，以便在围绕基板的热过程中对基板的损伤最小化。 构成：处理衬底的处理空间在室（100）内供应。 支撑单元（1000）支撑基板。 加热构件（200）加热基板。 多个支撑销（1040）从板向上突出。 至少一个子销（1060）从板向顶部突出。 支撑销位于子针脚周围。 （附图标记）（226）电源单元; （248）电源单元; （300）控制器

公开(公告)号：KR1020100018836A

公开(公告)日：2010-02-18

申请号：KR1020080077531

申请日：2008-08-07

Applicant: 삼성전자주식회사

Inventor： 류정도 ,  최시영 ,  신유균 ,  박태서 ,  김동찬 ,  유종렬 ,  정성훈 ,  강종훈

IPC: H01L21/336

CPC classification number: H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

Abstract: PURPOSE: An electrode of a semiconductor device and a method for manufacturing the same are provided to reduce contamination of a metal due to the diffusion of a metal atom by preventing the diffusion of the metal atom included in the metal material with a nitride layer. CONSTITUTION: A polysilicon film(102) doped with an impurity is formed on a substrate(100). A hard mask pattern is formed on the polysilicon layer. A pre-polysilicon pattern(106) is formed by etching the polysilicon layer with the hard mask pattern as an etching mask. The surface of the pre-polysilicon pattern is reacted with nitrogen and a nitride film(108) is formed on the surface of the pre-polysilicon pattern. A polysilicon film pattern(110) is formed by etching an exposed part of the pre-polysilicon pattern by the hard mask pattern.

Abstract translation: 目的：提供半导体器件的电极及其制造方法，以通过防止金属材料中包含的金属原子与氮化物层的扩散来减少由于金属原子扩散引起的金属污染。 构成：在衬底（100）上形成掺杂有杂质的多晶硅膜（102）。 在多晶硅层上形成硬掩模图案。 通过用硬掩模图案蚀刻多晶硅层作为蚀刻掩模来形成预多晶硅图案（106）。 预多晶硅图案的表面与氮反应，并且在多晶硅图案的表面上形成氮化物膜（108）。 通过硬掩模图案蚀刻预多晶硅图案的暴露部分来形成多晶硅膜图案（110）。

公开(公告)号：KR100843231B1

公开(公告)日：2008-07-02

申请号：KR1020070007250

申请日：2007-01-23

Applicant: 삼성전자주식회사

Inventor： 강종훈 ,  박태서 ,  최시영 ,  김미진

IPC: H01L21/26 ,  H01L21/265

CPC classification number: H01L21/2236 ,  H01L21/28035 ,  H01L21/3215 ,  H01L21/32155 ,  H01L29/4916

Abstract: A plasma doping method is provided to maintain a constant thickness of a doping target layer after a doping process by mixing an etch gas and a deposition gas. A semiconductor substrate is arranged in an inside of a chamber. A doping target layer having a first thickness is formed on the semiconductor substrate. A first gas supply process is performed to supply a first gas including components of a doping target layer onto the doping target layer. A second gas supply process is performed to supply a second gas including components for reducing the thickness of the doping target layer. The doping target layer includes polysilicon or a metal film. The first gas is composed of SiH4 gas. The second gas includes fluorine.

Abstract translation: 提供等离子体掺杂方法以通过混合蚀刻气体和沉积气体来在掺杂工艺之后保持掺杂目标层的恒定厚度。 半导体衬底布置在室的内部。 在半导体衬底上形成具有第一厚度的掺杂目标层。 执行第一气体供给处理以将包括掺杂目标层的成分的第一气体提供到掺杂目标层上。 执行第二气体供给处理以提供包括用于减小掺杂目标层的厚度的组分的第二气体。 掺杂靶层包括多晶硅或金属膜。 第一气体由SiH4气体组成。 第二气体包括氟。

公开(公告)号：KR1020080006750A

公开(公告)日：2008-01-17

申请号：KR1020060065871

申请日：2006-07-13

Applicant: 삼성전자주식회사

Inventor： 백계현 ,  강창진 ,  김용진 ,  강종훈

IPC: H01L21/265

Abstract: A plasma doping system for fabricating a semiconductor device is provided to prevent a process error by monitoring the abnormal state of a plasma doping process in a real-time period. A plasma doping system comprises a chamber, a platten for supporting a wafer within the chamber, and an RF generator for applying RF power. A voltage-current detection unit(260) is connected between the RF generator and the platten in order to detect the amount of changing voltage-current between the RF generator and the platten. An optical fiber(270) is installed at a view port of the chamber in order to detect the change of atmosphere of the chamber and the degassing state of a chamber wall. An RF detection unit(280) is installed at the view port in order to detect generation of arcs within the plasma and the change of the atmosphere within the chamber. A data processor(290) receives output signals from the voltage-current detection unit, the optical fiber, and the RF detection unit in order to determine the abnormal state of a plasma dipping process. A system controller(300) controls the plasma doping system on the basis of a determination signal of the data processor.

Abstract translation: 提供了一种用于制造半导体器件的等离子体掺杂系统，以通过在实时期间监测等离子体掺杂过程的异常状态来防止工艺误差。 等离子体掺杂系统包括腔室，用于支撑腔室内的晶片的平板，以及用于施加RF功率的RF发生器。 电压电流检测单元（260）连接在RF发生器和压板之间，以便检测在RF发生器和压板之间改变电压电流的量。 为了检测室的气氛变化和室壁的脱气状态，将光纤（270）安装在室的视口处。 为了检测等离子体内的电弧的产生和室内的气氛的变化，在检视口安装有RF检测部（280）。 数据处理器（290）从电压 - 电流检测单元，光纤和RF检测单元接收输出信号，以便确定等离子体浸渍处理的异常状态。 系统控制器（300）基于数据处理器的确定信号来控制等离子体掺杂系统。