公开(公告)号：KR1020100061064A

公开(公告)日：2010-06-07

申请号：KR1020080119942

申请日：2008-11-28

Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

Inventor： 박재철 ,  송이헌 ,  박영수 ,  권기원 ,  김창정 ,  김경국 ,  박성호 ,  이성훈 ,  김상욱 ,  김선일

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/1251

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to easily form as a low-temperature process by forming a first oxide channel layer and a second oxide channel layer into an oxide. CONSTITUTION: A first thin film transistor includes a first source(S10), a first drain, a first channel layer, and a first gate. A second thin film transistor includes a second source(S20), a second drain, a second channel layer, and a second gate. One is a p-type oxide layer among the first and the second channel layer. The first and the second thin film transistor is a bottom gate(BG10, BG20) structure or a top gate structure. One is a dual gate including more other gates among the first and the second thin film transistor at least.

Abstract translation: 目的：通过将第一氧化物沟道层和第二氧化物沟道层形成为氧化物，提供半导体器件及其制造方法以容易地形成为低温工艺。 构成：第一薄膜晶体管包括第一源（S10），第一漏极，第一沟道层和第一栅极。 第二薄膜晶体管包括第二源（S20），第二漏极，第二沟道层和第二栅极。 一个是第一和第二沟道层中的p型氧化物层。 第一和第二薄膜晶体管是底栅（BG10，BG20）结构或顶栅结构。 一个是至少包括第一和第二薄膜晶体管中的更多其它栅极的双栅极。

公开(公告)号：KR1020100055867A

公开(公告)日：2010-05-27

申请号：KR1020080114755

申请日：2008-11-18

Applicant: 삼성전자주식회사

Inventor： 김경국 ,  채수희 ,  박영수 ,  김택 ,  양문승 ,  정형수 ,  박재철 ,  김준연

IPC: H01L33/12 ,  H01L33/02

CPC classification number: H01L33/0079 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method for manufacturing a light emitting display is provided to reduce manufacturing costs of the light emitting device by performing a manufacturing process of the light emitting device at once after connecting several growth substrates on a bonding substrate with a large area. CONSTITUTION: A semiconductor layer with an active area for emission is formed on a growth substrate(11). A plurality of growth substrates with respective semiconductor layers are arranged on one bonding substrate(30). The plurality of semiconductor layers respectively formed on the plurality of growth substrates are simultaneously processed through a post-process. The surface of the growth substrate faces the bonding substrate and the growth substrate is bonded on the bonding substrate.

Abstract translation: 目的：提供一种制造发光显示器的方法，通过在大面积的接合基板上连接多个生长基板之后，一次进行发光器件的制造工艺来降低发光器件的制造成本。 构成：在生长衬底（11）上形成具有用于发射的有源区的半导体层。 具有各个半导体层的多个生长衬底被布置在一个接合衬底（30）上。 分别形成在多个生长衬底上的多个半导体层通过后处理同时进行处理。 生长衬底的表面面向接合衬底，生长衬底接合在接合衬底上。

公开(公告)号：KR1020100028412A

公开(公告)日：2010-03-12

申请号：KR1020080087439

申请日：2008-09-04

Applicant: 삼성전자주식회사

Inventor： 민복기 ,  박영수 ,  김택 ,  김준연

IPC: H01L33/18 ,  B82Y20/00

CPC classification number: H01L33/18 ,  B82Y20/00 ,  H01L33/405 ,  Y10S977/72 ,  Y10S977/721 ,  Y10S977/722 ,  Y10S977/723 ,  Y10S977/932

Abstract: PURPOSE: A light emitting diode using nano-rods and a method for manufacturing the same are provided to obtain the superior property of current diffusion and improve light emitting efficiency by preventing current crowding. CONSTITUTION: A light emitting diode(10) includes a carrier substrate(15), a reflective electrode(14), a plurality of nano-rods(12), a transparent insulation layer(13) and a transparent electrode(16). The reflective electrode is arranged on the carrier substrate. The nano-rods are perpendicularly arranged on the reflective electrode. The nano-rods include a first area, a second area and an active area. The transparent insulation layer is filled between the nano-rods. The transparent electrode is arranged on the nano-rods and the transparent insulation layer.

Abstract translation: 目的：提供使用纳米棒的发光二极管及其制造方法，以获得优异的电流扩散性能，通过防止电流拥挤而提高发光效率。 构成：发光二极管（10）包括载体基板（15），反射电极（14），多个纳米棒（12），透明绝缘层（13）和透明电极（16）。 反射电极设置在载体基板上。 纳米棒垂直布置在反射电极上。 纳米棒包括第一区域，第二区域和有源区域。 透明绝缘层填充在纳米棒之间。 透明电极布置在纳米棒和透明绝缘层上。

公开(公告)号：KR1020100002205A

公开(公告)日：2010-01-06

申请号：KR1020090057210

申请日：2009-06-25

Applicant: 삼성전자주식회사

Inventor： 김기환 ,  박영수 ,  이정현 ,  김창정 ,  강보수

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: PURPOSE: A memory device and a manufacturing method of the same are provided to prevent the deterioration of a memory device and a switch structure by forming an insulating layer since a source does not include hydrogen. CONSTITUTION: In a memory device and a manufacturing method of the same, a first electrode(11) is formed. Memory nodes(12, 14) are formed on the first electrode. An insulating layer is contacted to the memory node and is formed with a source material without hydrogen. The second electrode(13) is formed on the memory node. The memory node is formed with a transition metal oxide having the resistance change property.

Abstract translation: 目的：提供一种存储器件及其制造方法，用于通过形成绝缘层来防止存储器件和开关结构的劣化，因为源不包括氢。 构成：在存储器件及其制造方法中，形成第一电极（11）。 存储器节点（12,14）形成在第一电极上。 绝缘层与存储器节点接触并且形成有不含氢的源材料。 第二电极（13）形成在存储器节点上。 记忆节点形成有具有电阻变化特性的过渡金属氧化物。

公开(公告)号：KR1020090123080A

公开(公告)日：2009-12-02

申请号：KR1020080048974

申请日：2008-05-27

Applicant: 삼성전자주식회사

Inventor： 박영수 ,  이근호

IPC: H04B7/26 ,  H04W4/06 ,  H04W4/02

CPC classification number: H04H20/72 ,  H04H60/15 ,  H04W4/06 ,  H04W76/40 ,  H04W12/06 ,  H04W24/00

Abstract: PURPOSE: An information service device in the wireless communication system and a method thereof are provided to offer a discriminated information service to a user by enabling a base station to transmit information specialized to a region to registered terminals. CONSTITUTION: Information for shops located in a cell region is received from a network entity of the core service network(201). The received shop information is classified and stored in a database(203). Multicast connection IDs are allocated and a transmission cycle is checked. If a transmitting time according to the transmission cycle is arrived, a shop list of a corresponding category is obtained. An advertisement multicast burst including the shop list is composed.

Abstract translation: 目的：提供无线通信系统中的信息服务设备及其方法，通过使基站能够将专用于区域的信息发送到注册终端，向用户提供鉴别信息服务。 构成：从核心服务网络（201）的网络实体接收位于小区区域内的商店的信息。 接收到的商店信息被分类并存储在数据库（203）中。 分配组播连接ID并检查传输周期。 如果到达根据传输周期的发送时间，则获得相应类别的商店列表。 构成包括商店列表的广播组播突发。

公开(公告)号：KR1020090103610A

公开(公告)日：2009-10-01

申请号：KR1020080029327

申请日：2008-03-28

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박영수 ,  박재철

IPC: H01L27/04 ,  H01L29/786

CPC classification number: H01L21/823462 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/1225

Abstract: PURPOSE: An inverter is provided to perform an existing CMOS inverter property and to simplify a manufacturing process. CONSTITUTION: An inverter includes a depletion mode load transistor(T1), an enhancement mode driving transistor(T2), and a barrier layer. The depletion mode load transistor has a first oxide layer as a channel layer. The enhancement mode driving transistor is connected to the load transistor, and has a second oxide layer as a channel layer. The barrier layer is formed between a source electrode and a drain electrode corresponding to the second oxide layer.

Abstract translation: 目的：提供逆变器来执行现有的CMOS反相器特性，并简化制造过程。 构成：逆变器包括耗尽型负载晶体管（T1），增强型驱动晶体管（T2）和阻挡层。 耗尽型负载晶体管具有作为沟道层的第一氧化物层。 增强型驱动晶体管连接到负载晶体管，并具有作为沟道层的第二氧化物层。 在与第二氧化物层对应的源电极和漏电极之间形成阻挡层。

公开(公告)号：KR1020090058952A

公开(公告)日：2009-06-10

申请号：KR1020070125767

申请日：2007-12-05

Applicant: 삼성전자주식회사

Inventor： 김경국 ,  김주성 ,  박영수

IPC: H01L33/00 ,  B82Y20/00

CPC classification number: H01L33/08 ,  B82Y20/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/0262 ,  H01L33/34

Abstract: A light emitting device and a method for manufacturing the same are provided to implement the light emitting device stably by using a nano-rod or nano-wire. A first electrode layer(12) is formed on a substrate(10). A bottom layer(14) is formed on the first electrode layer. A plurality of nano-rods(23) are vertically formed on the bottom layer. The nano-rode includes a first type doped lower unit, a second type doped upper unit, and an active layer between the lower unit and the upper unit. An insulation region(24) is formed between nano-rods. A second electrode layer(26) is formed on the insulation region and the nano-rod.

Abstract translation: 提供一种发光器件及其制造方法，通过使用纳米棒或纳米线来稳定地实现发光器件。 第一电极层（12）形成在基板（10）上。 底层（14）形成在第一电极层上。 多个纳米棒（23）垂直地形成在底层上。 纳米罗盘包括第一类掺杂下单元，第二类掺杂上单元和下单元与上单元之间的有源层。 在纳米棒之间形成绝缘区域（24）。 第二电极层（26）形成在绝缘区域和纳米棒上。

公开(公告)号：KR1020090039064A

公开(公告)日：2009-04-22

申请号：KR1020070104476

申请日：2007-10-17

Applicant: 삼성전자주식회사

Inventor： 임혁 ,  박영수 ,  강동훈 ,  후아샹잉 ,  김상욱

IPC: H01L29/786

CPC classification number: H01L29/78648 ,  H01L29/7869

Abstract: A transistor and an operation method thereof are provided to improve degradation of an operation speed of a transistor due to damage of a channel layer by using a second gate electrode which increases a sub threshold voltage tilt. A first gate electrode(110) is formed on a top of a substrate(100). A first gate insulation layer(120) is formed on a top of the substrate including the first gate electrode. A channel layer(130) is formed on a top of the first gate insulation layer on the first gate electrode. A source electrode(140a) and a drain electrode(140b) are formed in both ends of the channel layer. A second gate insulation layer(150) for covering the source electrode, the drain electrode, and the channel layer is formed on a top of the first gate insulation layer. A second gate electrode(160) is formed on a top of the second gate insulation layer.

Abstract translation: 提供晶体管及其操作方法，以通过使用增加副阈值电压倾斜的第二栅电极来改善由于沟道层的损坏导致的晶体管的操作速度的劣化。 第一栅电极（110）形成在基板（100）的顶部上。 在包括第一栅电极的基板的顶部上形成第一栅极绝缘层（120）。 沟道层（130）形成在第一栅电极上的第一栅极绝缘层的顶部上。 源极电极（140a）和漏电极（140b）形成在沟道层的两端。 用于覆盖源电极，漏电极和沟道层的第二栅极绝缘层（150）形成在第一栅极绝缘层的顶部上。 第二栅极电极（160）形成在第二栅极绝缘层的顶部上。

公开(公告)号：KR1020090029558A

公开(公告)日：2009-03-23

申请号：KR1020070094898

申请日：2007-09-18

Applicant: 삼성전자주식회사

Inventor： 겐리치스테파노비치 ,  강보수 ,  박영수 ,  선우문욱 ,  이명재 ,  안승언 ,  이창범

IPC: H01L29/861

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/24 ,  H01L29/242 ,  H01L29/267 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A diode and a memory device comprising the same are provided to implement the high integration of memory device by increasing the forward current density of N-type and P-type semiconductor layers. A diode(100) comprises the resistance alteration material. The resistance alteration material comprises either P-type or N-type semiconductor layer(10,20). The resistance of the resistance alteration material is changed according to the applied voltage. The memory device comprises the diode and the storage node. The diode has the resistance alteration material in either P-type or N-type semiconductor layer.

Abstract translation: 提供二极管和包括该二极管的存储器件以通过增加N型和P型半导体层的正向电流密度来实现存储器件的高集成度。 二极管（100）包括电阻改变材料。 电阻改变材料包括P型或N型半导体层（10,20）。 电阻变化材料的电阻根据施加的电压而改变。 存储器件包括二极管和存储节点。 二极管具有P型或N型半导体层中的电阻改变材料。

公开(公告)号：KR1020090018504A

公开(公告)日：2009-02-20

申请号：KR1020070082989

申请日：2007-08-17

Applicant: 삼성전자주식회사

Inventor： 강보수 ,  겐리치스테파노비치 ,  박영수 ,  이명재 ,  안승언 ,  이창범

IPC: H01L29/86 ,  H01L29/861

CPC classification number: H01L29/242 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/24 ,  H01L29/267 ,  H01L29/8618

Abstract: A diode structure and a memory device including the same are provided to obtain a high rectifying characteristic by increasing a forward/backward current ratio and a forward current density. A diode structure includes a first electrode(11), a p-type Cu oxide layer(12), an n-type InZn oxide layer(13) and a second electrode(14). The p-type Cu oxide layer is formed on the first electrode. The n-type InZn oxide layer is formed on the p-type Cu oxide layer. The second electrode is formed on the n-type InZn oxide. The p-type Cu oxide layer includes CuO. The n-type InZn oxide layer includes InZnO. The first electrode and the second electrode are made of metal or conductive metal oxide. The diode structure is formed by a PVD(Physical Vapor Deposition), an ALD(Atomic Layer Deposition) or a CVD(Chemical Vapor Deposition) method.

Abstract translation: 提供二极管结构和包括该二极管结构的存储器件以通过增加正向/反向电流比和正向电流密度来获得高整流特性。 二极管结构包括第一电极（11），p型Cu氧化物层（12），n型InZn氧化物层（13）和第二电极（14）。 p型Cu氧化物层形成在第一电极上。 n型InZn氧化物层形成在p型Cu氧化物层上。 第二电极形成在n型InZn氧化物上。 p型Cu氧化物层包括CuO。 n型InZn氧化物层包括InZnO。 第一电极和第二电极由金属或导电金属氧化物制成。 二极管结构由PVD（物理气相沉积），ALD（原子层沉积）或CVD（化学气相沉积）法形成。