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    21.
    发明专利
    未知

    公开(公告)号：AT438926T

    公开(公告)日：2009-08-15

    申请号：AT02796462

    申请日：2002-08-29

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  LEAS JAMES ,  MA WILLIAM ,  RABIDOUX PAUL

    IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    22.
    发明专利
    未知

    公开(公告)号：AT398834T

    公开(公告)日：2008-07-15

    申请号：AT05717124

    申请日：2005-03-22

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  KOBURGER III ,  SLINKMAN JAMES

    IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

    Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME.
    23.
    发明专利
    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME. 未知

    公开(公告)号：MY121099A

    公开(公告)日：2005-12-30

    申请号：MYPI9904205

    申请日：1999-09-29

    Applicant: IBM

    Inventor： ALLEN ARCHIBALD J ,  FURUKAWA TOSHIHARU ,  O'NEIL EDWARD F ,  HAKEY MARK C ,  VERHELST ROGER A ,  HORAK DAVID V

    IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/11

    Abstract: THE PRESENT INVENTION OVERCOMES THE DIFFICULTIES FOUND IN THE BACKGROUND ART BY PROVIDING A DIRECT LOW RESISTIVE CONTACT (101, 102) BETWEEN DEVICES ON A SEMICONDUCTOR CHIP WITHOUT EXCESSIVE CURRENT LEAKAGE. CURRENT LEAKAGE IS PREVENTED IN THE PREFERRED DESIGN BY USING SILICON ON INSULATOR (SOI) CONSTRUCTION FOR THE CHIP. BY CONSTRUCTING THE DIRECT CONTACT OVER AN INSULATOR, SUCH AS SILICON DIOXIDE, CURRENT LEAKAGE IS MINIMIZED. THE PREFERRED EMBODIMENT USES SILICIDE (145, 147) TO CONNECT A POLYSILICON GATE (120, 122) TO A DOPED REGION (230, 235, 237, 830, 835, 837) OF THE SUBSTRATE. AN ALTERNATIVE EMBODIMENT OF THE PRESENT INVENTION PROVIDES FOR THE USE OF CONDUCTIVE STUDS (1910, 1920) TO ELECTRICALLY CONNECT DEVICES. AN INCREASED DENSITY OF APPROXIMATELY TWENTY PERCENT MAY BE REALIZED USING THE PRESENT INVENTION.

    A METHOD FOR FORMING SELF-ALIGNED FEATURES
    25.
    发明专利
    A METHOD FOR FORMING SELF-ALIGNED FEATURES 未知

    公开(公告)号：MY118631A

    公开(公告)日：2004-12-31

    申请号：MYPI9904305

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/4763 ,  H01L21/027 ,  H01L21/768

    Abstract: THE PRESENT INVENTION PROVIDES FOR AN IMPROVED METHOD OF CREATING VIAS (730, 735) AND TRENCHES (737-739) DURING MICROCHIP FABRICATION. ACCORDING TO THE INVENTION, THE VIAS AND TRENCHES ARE SELF-ALIGNED DURING THE PHOTOLITHOGRAPHY PROCESS BY USING TWO LAYERS OF SPECIALLY SELECTED RESISTS (205, 210, 1804, 1806) AND EXPOSING THE RESISTS SUCH THAT THE LOWER RESIST IS EXPOSED ONLY WHERE AN OPENING HAS BEEN FORMED IN THE UPPER RESIST LAYER. THIS SELF-ALIGNING ENABLES THE VIAS TO BE PRINTED AS ELONGATED SHAPES, WHICH ALLOWS FOR THE USE OF PARTICULARLY EFFECTIVE IMAGE ENHANCEMENT TECHNIQUES. THE INVENTION FURTHER PROVIDES A SIMPLIFIED PROCEDURE FOR CREATING VIAS AND TRENCHES, IN THAT ONLY ONE ETCH STEP IS REQUIRED TO SIMULTANEOUSLY CREATE BOTHVIAS AND TRENCHES. AN ALTERNATIVE EMBODIMENT OF THE INVENTION ALLOWS LOOPED OR LINKED IMAGES, SUCH AS THOSE PRINTED USING IMAGE ENHANCEMENT TECHNIQUES, TO BE TRIMMED TO FORM ISOLATED FEATURES.

    28.
    发明专利
    未知

    公开(公告)号：AT504942T

    公开(公告)日：2011-04-15

    申请号：AT05737717

    申请日：2005-02-23

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HORAK DAVID ,  KOBURGER III CHARLES ,  MASTERS MARK ,  MITCHELL PETER ,  POLONSKY STANISLAV

    IPC: H01L21/768 ,  H01L21/285 ,  H01L23/522

    Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

    29.
    发明专利
    未知

    公开(公告)号：DE602005007592D1

    公开(公告)日：2008-07-31

    申请号：DE602005007592

    申请日：2005-03-22

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  KOBURGER III CHARLES ,  SLINKMAN JAMES ALBERT

    IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

    Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

    30.
    发明专利
    未知

    公开(公告)号：AT389242T

    公开(公告)日：2008-03-15

    申请号：AT05701511

    申请日：2005-01-13

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MITCHELL PETER ,  NESBIT LARRY

    IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

    Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

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