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    Hybride Photoresistzusammensetzung sowie musterbildendes Verfahren unter Verwendung derselben
    21.
    发明专利
    Hybride Photoresistzusammensetzung sowie musterbildendes Verfahren unter Verwendung derselben 未知

    公开(公告)号：DE112012004718T5

    公开(公告)日：2014-08-07

    申请号：DE112012004718

    申请日：2012-11-02

    Applicant: IBM

    Inventor： CHEN KUANG-JUNG ,  HUANG WU-SONG ,  HOLMES STEVEN J ,  BREYTA GREGORY ,  LIU SEN

    IPC: G03F7/004 ,  G03F7/028 ,  G03F7/11 ,  G03F7/26 ,  H01L21/027

    Abstract: Die vorliegende Erfindung bezieht sich auf eine hybride Photoresistzusammensetzung für eine verbesserte Auflösung sowie auf ein musterbildendes Verfahren unter Verwendung der Photoresistzusammensetzung. Die Photoresistzusammensetzung beinhaltet einen strahlungsempfindlichen Säuregenerator, ein quervernetzendes Agens sowie ein Polymer mit einer hydrophoben Monomer-Einheit und einer hydrophilen Monomer-Einheit, die eine Hydroxyl-Gruppe enthält. Wenigstens einige der Hydroxyl-Gruppen sind mit einer säurelabilen funktionellen Gruppe mit einer niedrigen Aktivierungsenergie geschützt. Das Photoresist ist in der Lage, eine hybride Reaktion auf eine einzelne Belichtung zu erzeugen. Das musterbildende Verfahren verwendet die hybride Reaktion, um eine Struktur mit Muster in der Photoresistschicht zu bilden. Die Photoresistzusammensetzung und das musterbildende Verfahren der vorliegenden Erfindung sind nützlich, um kleine Elemente mit einer präzisen Abbildungssteuerung zu drucken, im Besonderen Zwischenräume mit geringen Abmessungen.

    22.
    发明专利
    未知

    公开(公告)号：DE60233241D1

    公开(公告)日：2009-09-17

    申请号：DE60233241

    申请日：2002-08-29

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

    IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING
    23.
    发明专利
    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING 未知

    公开(公告)号：MY117201A

    公开(公告)日：2004-05-31

    申请号：MYPI9904530

    申请日：1999-10-20

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: G03C5/00 ,  H01L21/28 ,  H01L21/027 ,  H01L21/302 ,  H01L21/32 ,  H01L21/60 ,  H01L21/768

    Abstract: A METHOD FOR FORMING CONTACTS ON AN INTEGRATED CIRCUIT THAT ARE SELF-ALIGNED WITH THE WIRING PATTERNS OF THE INTEGRATED CIRCUIT. IN THE METHOD A THICKER LOWER LAYER (12) OF A FIRST MATERIAL AND A THINNER UPPER LAYER (14) OF A SECOND MATERIAL ARE FORMED ON A SUBSTRATE (10). THE FEATURES OF THE METAL WIRING IS PATTERNED FIRST ON THE UPPER LAYER. THE WIRING PATTERN TRENCHES (20) ARE ETCHED THROUGH THE THINNER SURFACE LAYER, AND PARTIALLY THROUGH THE SECOND, THICKER LAYER. AFTER THE WIRING PATTERN IS ETCHED, THE CONTACTS FOR THE WIRING LAYER ARE PRINTED AS LINE/SPACE PATTERNS WHICH INTERSECT THE WIRING PATTERN. THE CONTACT PATTERN IS ETCHED INTO THE LOWER, THICKER LAYER WITH AN ETCH PROCESS THAT IS SELECTIVE TO THE UPPER THINNER LAYER. THE CONTACT IS ONLY FOFFI1ED AT THE INTERSECTION POINT OF THE WIRING IMAGE WITH THE CONTACT IMAGE, THEREFORE THE CONTACT IS SELF-ALIGNED TO THE METAL (24).

    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY
    26.
    发明专利
    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY 未知

    公开(公告)号：MY117065A

    公开(公告)日：2004-04-30

    申请号：MYPI9904306

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/22 ,  H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78

    Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FORMING SELF-ALIGNED SPACERS (502) ON THE HORIZONTAL SURFACES WHILE REMOVING SPACER MATERIAL FROM THE VERTICAL SURFACES. THE PREFERRED METHOD USES A RESIST(302) THAT CAN BE MADE INSOLUBLE TO DEVELOPER BY THE USE OF AN IMPLANT. BY CONFORMALLY DEPOSITING THE RESIST OVER A SUBSTRATE (202) HAVING BOTH VERTICAL AND HORIZONTAL SURFACES, IMPLANTING THE RESIST, AND DEVELOPING THE RESIST, THE RESIST IS REMOVED FROM THE VERTICAL SURFACES WHILE REMAINING ON THE HORIZONTAL SURFACES. THUS, A SELF-ALIGNED SPACER IS FORMED ON THE HORIZONTAL SURFACES WHILE THE SPACER MATERIAL IS REMOVED FROM THE VERTICAL SURFACES. THIS HORIZONTAL-SURFACE SPACER CAN THEN BE USED IN FURTHER FABRICATION. THE PREFERRED METHOD CAN BEUSED IN MANY DIFFERENT PROCESSES WHERE THERE IS EXISTS A NEED TO DIFFERENTIALLY PROCESS THE VERTICAL AND HORIZONTAL SURFACES OF A SUBSTRATE.FIG. 1

    Dual hard mask lithography process
    29.
    发明专利
    Dual hard mask lithography process 未知

    公开(公告)号：GB2511456A

    公开(公告)日：2014-09-03

    申请号：GB201410024

    申请日：2012-12-20

    Applicant: IBM

    Inventor： BURNS SEAN D ,  HOLMES STEVEN J ,  HORAK DAVID V ,  SANKARAPANDIAN MUTHUMANICKAM ,  YIN YUNPENG ,  ARNOLD JOHN C

    IPC: H01L21/033 ,  G03F7/00 ,  H01L21/768

    Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

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