公开(公告)号：DE3175419D1

公开(公告)日：1986-11-06

申请号：DE3175419

申请日：1981-10-20

Applicant: IBM

Inventor： GRISE GARY DOUGLAS ,  HSIEH NING ,  KALTER HOWARD LEO ,  LAM CHUNG HON

IPC: G11C14/00 ,  G11C11/34 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

Abstract: A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1, T3) includes an enhanced conduction insulator (24) and means (T1-T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).

公开(公告)号：DE2351523A1

公开(公告)日：1974-05-16

申请号：DE2351523

申请日：1973-10-13

Applicant: IBM

Inventor： ANDERSON JUN ROBERT DOUGLAS ,  BEHMAN STEPHEN BARRY ,  KALTER HOWARD LEO ,  GOLDSTEIN STEPHEN

IPC: G11C11/406 ,  G11C7/00 ,  G06F13/06 ,  G11C11/24

公开(公告)号：SG46485A1

公开(公告)日：1998-02-20

申请号：SG1996005030

申请日：1990-02-02

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE69119258T2

公开(公告)日：1996-11-21

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE69119258D1

公开(公告)日：1996-06-13

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE68923811D1

公开(公告)日：1995-09-21

申请号：DE68923811

申请日：1989-03-09

Applicant: IBM

Inventor： FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  MILLER CHRISTOPHER PAUL ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

公开(公告)号：DE69019665D1

公开(公告)日：1995-06-29

申请号：DE69019665

申请日：1990-09-07

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：NZ232466A

公开(公告)日：1992-08-26

申请号：NZ23246690

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/16 ,  G11C29/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：AU623490B2

公开(公告)日：1992-05-14

申请号：AU4939390

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/00 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：AU6232790A

公开(公告)日：1991-04-18

申请号：AU6232790

申请日：1990-09-10

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/0175

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.