公开(公告)号：IL297096A

公开(公告)日：2022-12-01

申请号：IL29709622

申请日：2022-10-06

Applicant: IBM ,  RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG SHENG KANG

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: B82Y10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：GB2595098B

公开(公告)日：2022-10-26

申请号：GB202110765

申请日：2019-12-02

Applicant: IBM

Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

IPC: H01L21/02

Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

公开(公告)号：GB2604510A

公开(公告)日：2022-09-07

申请号：GB202207100

申请日：2020-10-16

Applicant: IBM

Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  KANGGUO CHENG ,  HENG WU

IPC: H01L27/11 ,  G11C11/417 ,  H01L27/11517 ,  H01L27/11551

Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

公开(公告)号：GB2600316A

公开(公告)日：2022-04-27

申请号：GB202200795

申请日：2020-06-15

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

IPC: H01L29/00 ,  H10B10/00

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

公开(公告)号：GB2595098A

公开(公告)日：2021-11-17

申请号：GB202110765

申请日：2019-12-02

Applicant: IBM

Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

IPC: H01L21/02

Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

公开(公告)号：GB2582087A

公开(公告)日：2020-09-09

申请号：GB202007421

申请日：2018-12-03

Applicant: IBM

Inventor： JUNTAO LI ,  KANGGUO CHENG ,  LIYING JLANG ,  JOHN GERARD GAUDIELLO

IPC: H01L21/84

Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under- layer segment and second vertical fin on the second region.

公开(公告)号：GB2579533A

公开(公告)日：2020-06-24

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

公开(公告)号：GB2494338B

公开(公告)日：2014-06-11

申请号：GB201221985

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.

公开(公告)号：GB2607481B

公开(公告)日：2025-02-05

申请号：GB202211293

申请日：2020-12-23

Applicant: IBM

Inventor： RUILONG XIE ,  KANGGUO CHENG ,  JULIEN FROUGIER

IPC: H01L21/768 ,  H01L23/485 ,  H10D30/43 ,  H10D30/67 ,  H10D48/36 ,  H10D62/10 ,  H10D62/13 ,  H10D64/27 ,  H10D84/03 ,  H10D84/83

Abstract: Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.

公开(公告)号：GB2628728A

公开(公告)日：2024-10-02

申请号：GB202408798

申请日：2022-11-28

Applicant: IBM

Inventor： LAN YU ,  KANGGUO CHENG ,  HENG WU ,  CHEN ZHANG

IPC: H01L29/66

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.