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    CAPACITOR STORAGE MEMORY
    23.
    发明专利
    CAPACITOR STORAGE MEMORY 未知

    公开(公告)号：CA1095621A

    公开(公告)日：1981-02-10

    申请号：CA274093

    申请日：1977-03-16

    Applicant: IBM

    Inventor： PRICER WILBUR D

    IPC: G11C11/24

    Abstract: CAPACITOR STORAGE MEMORY A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a word pulse again connects the charge source with each of the capacitors.

    24.
    发明专利
    未知

    公开(公告)号：DD141082A5

    公开(公告)日：1980-04-09

    申请号：DD20634778

    申请日：1978-06-28

    Applicant: IBM

    Inventor： JOSHI MADHUKAR L ,  PRICER WILBUR D

    IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/40

    Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME
    28.
    发明专利
    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME 未知

    公开(公告)号：HK1026064A1

    公开(公告)日：2000-12-01

    申请号：HK00105169

    申请日：2000-08-17

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

    IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

    Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

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