公开(公告)号：DE102005048826B3

公开(公告)日：2007-04-12

申请号：DE102005048826

申请日：2005-10-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  CHAN KAI CHONG

IPC: H01L21/301 ,  H01L21/50 ,  H01L21/78

Abstract: The semiconductor component comprises a semi conductor wafer (10) placed by its back onto a support foil (13). Interstices (14) are formed along the chip positions on the top side (15) of the wafer but do not break right through. The wafer is applied to the wafer carrier and layered from the back to the interstices. A pretensioned adhesive foil or shrink foil is applied to the back of the wafer and heated. The chips and adhesive foil are removed from the wafer carrier and the contact faces on the top of the chip are connected to the contact connectors of the circuit carrier through connecting elements. The connecting elements, chips with the back foil and circuit carrier are packed in a plastics housing and the circuit carrier is divided into individual semi conductor components. Several semiconductor chips are produced where the wafer is made with several chip positions arranged in columns and rows.

公开(公告)号：DE102005038956B3

公开(公告)日：2007-03-22

申请号：DE102005038956

申请日：2005-08-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  STROBEL PETER ,  POHL JENS ,  STUEMPFL CHRISTIAN ,  HEITZER LUDWIG

IPC: H01L21/58

Abstract: Coating wafer level package structure (1) with a semiconductor chip (4) comprises applying coating particles (5) on a substrate (6), electrostatic charging of the substrate and the particles, and liquefying the particles by heating the coating particles surface (7). The structure is electrostaticlly charged with chip to a polarity opposite to that of the substrate. The substrate and structure are moved in the direction of the surface of the coated structure until the coating particles jump on to the surface of the coated structure and cling on to it. The coating wafer level package structure (1) with semiconductor chip (4), comprises applying coating particles (5) on a substrate (6), electrostatic charging of substrate and the particles, and liquefying the particles by heating coating particles surface (7). The structure is electrostaticlly charged with chip to a polarity opposite to that of the substrate. The substrate and structure are moved in the direction of the surface of the coated structure until the coating particles jump on to the surface of the coated structure and cling on to it. Nano-particles, filled polymers, metals, and organometallic compounds are used as coating particles. The wafer level package exhibits a multiplicity of semiconductor chips that lie at the same level and plastic regions that are present between the semiconductor chips. Another substrate with straticulated semiconductor chips is electrostatically charged. The electrically conducting surfaces of the structure are coated with an adhesion mediator layer during the preparation of the electrostatic separation. A metal-coated plate is used as the substrate. The substrate is aligned horizontally with its side exhibiting the coating particles. A multi-layer coating is led over substrates with different coating particles. A melting up of the coating particles takes place between each run of coating.

公开(公告)号：DE102005043557B4

公开(公告)日：2007-03-01

申请号：DE102005043557

申请日：2005-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUNNBAUER MARKUS ,  FUERGUT EDWARD ,  POHL JENS ,  BAUER MICHAEL ,  HEITZER LUDWIG

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/60 ,  H01L25/065

公开(公告)号：DE102005023949A1

公开(公告)日：2006-11-30

申请号：DE102005023949

申请日：2005-05-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  VILSMEIER HERMANN ,  JEREBIC SIMON ,  BAUER MICHAEL ,  BEMMERL THOMAS

IPC: H01L23/04 ,  H01L21/60 ,  H01L23/50

Abstract: The invention relates to a panel and a semiconductor device including a composite plate with semiconductor chips and a plastic packaging compound, and to processes for producing them. For this purpose, the panel having a composite plate has semiconductor chips arranged in rows and columns on a top side of a wiring substrate. The wiring substrate is covered by a plastic packaging compound in a plurality of semiconductor device positions, the rear sides of the semiconductor chips being fixed on the wiring substrate. A plastic packaging compound in the region of the boundary surfaces with the semiconductor chips has a coefficient of thermal expansion which is matched to that of silicon, while the remaining plastic packaging compound has a coefficient of thermal expansion which is matched to that of the wiring substrate and is therefore correspondingly higher.

公开(公告)号：DE102005010272A1

公开(公告)日：2006-09-14

申请号：DE102005010272

申请日：2005-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAHLER JOACHIM ,  HAIMERL ALFRED ,  SCHOBER WOLFGANG ,  BAUER MICHAEL ,  KESSLER ANGELA

IPC: H01L21/56 ,  H01L21/60

Abstract: Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam.

公开(公告)号：DE102004040414B4

公开(公告)日：2006-08-31

申请号：DE102004040414

申请日：2004-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WOERNER HOLGER ,  BAUER MICHAEL ,  STEINER RAINER

IPC: H01L23/50 ,  H01L21/60 ,  H05K1/00 ,  H05K3/00

Abstract: A wiring substrate of a semiconductor component includes: an underside with a wiring structure; a top side with cutouts; a rubber-elastic material arranged in the cutouts; and external contact pads arranged on the rubber-elastic material and configured to be coupled to external contacts. A method for producing a wiring substrate of this type, involves pressing the rubber-elastic material pads into a precursor of a polymer plastic during the production process.

公开(公告)号：DE102004059233A1

公开(公告)日：2006-06-14

申请号：DE102004059233

申请日：2004-12-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  KESSLER ANGELA ,  SCHOBER WOLFGANG ,  HAIMERL ALFRED ,  MAHLER JOACHIM

IPC: H01L23/28 ,  G02B6/122 ,  G02B6/13 ,  H01L31/0203

Abstract: Production of an optical structure comprises encasing a semiconductor component (1) with an optically transparent material which is opaque to a high energy beam and irradiating each region of the sleeve (6) produced with high energy radiation. An independent claim is also included for an encased semiconductor component.

公开(公告)号：DE102004048201A1

公开(公告)日：2006-04-13

申请号：DE102004048201

申请日：2004-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAHLER JOACHIM ,  HAIMERL ALFRED ,  SCHOBER WOLFGANG ,  BAUER MICHAEL ,  HOSSEINI KHALIL ,  KESSLER ANGELA

IPC: H01L23/10 ,  B82B3/00 ,  C01B31/00 ,  C08J5/24 ,  C09C1/44 ,  C09D5/25 ,  C09J5/06 ,  H01L21/56 ,  H01L21/58

Abstract: A layer improves adhesion between interfaces of different components in semiconductor devices. The interface of a first component includes surfaces of a circuit carrier and the interface of a second component includes contact surfaces of a plastic package molding compound. The adhesion-improving layer includes a mixture of polymeric chain molecules and carbon nanotubes.

公开(公告)号：DE102004044603A1

公开(公告)日：2006-03-30

申请号：DE102004044603

申请日：2004-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WOERNER HOLGER ,  BAUER MICHAEL

IPC: H01L23/29 ,  H01L23/50

Abstract: A surface mountable semiconductor component comprises a plastic housing (2) with solder spheres (3) as outer contacts (4) on the bottom (5). A filling material is located at the bottom and covers the edge region (8) of the lower section. The material comprises a synthetic region comprising a base polymer and a hardener. The hardener is located in numerous capsules.

公开(公告)号：DE102004036909A1

公开(公告)日：2006-03-23

申请号：DE102004036909

申请日：2004-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POHL JENS ,  WOERNER HOLGER ,  STEINER RAINER ,  VILSMEIER HERMANN ,  BAUER MICHAEL ,  ZUHR BERNHARD ,  BACHMAIER ULRICH ,  HAGEN ROBERT

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/60 ,  H01L25/065

Abstract: A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate, which is electrically connected by way of the wiring substrate on the one hand to external contacts on the underside of the wiring substrate and on the other hand to contact terminal areas in the edge regions of the wiring substrate. The intermediate wiring board has angled-away external flat conductors, which are electrically connected in the contact terminal areas of the wiring board. Furthermore, on the upper side of the intermediate wiring board, arranged on the free ends of the internal flat conductors are external contact terminal areas, which correspond in size and arrangement to external contacts of a semiconductor device to be stacked.