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    24.
    发明专利
    未知

    公开(公告)号：DE10345475B4

    公开(公告)日：2008-04-17

    申请号：DE10345475

    申请日：2003-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

    IPC: H01L27/115 ,  G03G15/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

    25.
    发明专利
    未知

    公开(公告)号：DE69834686T2

    公开(公告)日：2007-05-31

    申请号：DE69834686

    申请日：1998-03-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

    IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

    Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

    27.
    发明专利
    未知

    公开(公告)号：DE10128718B4

    公开(公告)日：2005-10-06

    申请号：DE10128718

    申请日：2001-06-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  ALSMEIER JOHANN

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A memory cell has a selection transistor and a trench capacitor. An upper capacitor electrode of the trench capacitor, in the region of an insulating collar, has a metallic section, and that section of the upper electrode that makes contact with a storage dielectric is of a non-metallic form, in particular containing polysilicon. A buried strap, which connects the upper electrode to the select transistor, is of a non-metallic form, in particular formed of polysilicon.

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