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    25.
    发明专利
    未知

    公开(公告)号：DE112004001244T5

    公开(公告)日：2006-06-01

    申请号：DE112004001244

    申请日：2004-06-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  SHUM DANNY PAK-CHUM ,  TEMPEL GEORG

    IPC: H01L27/115 ,  G11C16/02 ,  H01L21/8247

    Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14 . The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

    26.
    发明专利
    未知

    公开(公告)号：DE10245153A1

    公开(公告)日：2004-04-15

    申请号：DE10245153

    申请日：2002-09-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78

    Abstract: A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.

    28.
    发明专利
    未知

    公开(公告)号：DE59704305D1

    公开(公告)日：2001-09-20

    申请号：DE59704305

    申请日：1997-03-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD

    IPC: H01L29/66 ,  H01L21/336 ,  H01L29/739 ,  H01L29/788 ,  H01L29/861

    Abstract: The component has a channel zone and an oppositely doped zone in a semiconductor substrate. The channel zone and a peripheral region of the first doped zone are separated by a gate dielectric from an overlying channel gate electrode. The first doped zone is predominantly separated by a tunnel dielectric from an overlying tunnel gate electrode. When a suitable voltage is applied to the first doped zone, the tunnel current from the tunnel gate electrode generates an avalanche breakdown in the semiconductor substrate. A current results between the terminals of the channel zone and the first doped zones that is amplified by several orders of magnitude.

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