公开(公告)号：DE10255117A1

公开(公告)日：2004-06-17

申请号：DE10255117

申请日：2002-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  WERNER WOLFGANG ,  KLOSE HELMUT

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/112 ,  H01L21/8246

Abstract: A semiconductor memory device with a phase transformation memory effect includes at least one memory element in a semiconductor substrate, and a cavity arrangement including at least one cavity in spatial proximity to the respective memory element. The cavity is in spatial arrangement with the respective memory element so as to reduce thermal coupling of the respective memory element to the areas surrounding the memory element, which also reduces the thermal conductivity between memory element and the areas surrounding the memory element.

公开(公告)号：DE10212962A1

公开(公告)日：2003-10-16

申请号：DE10212962

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L51/20 ,  H01L51/30 ,  G11C11/21

Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

公开(公告)号：DE10212926A1

公开(公告)日：2003-10-16

申请号：DE10212926

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C11/56 ,  G11C13/02 ,  H01L27/10 ,  H01L29/78 ,  H01L27/115

Abstract: Semiconductor storage cell has a modulation region (M) arranged between first gate electrode (G1) of gate electrode arrangement,and an insulating region. (M) is made from a material which can be controllably modulated with respect to its electrical and/or its wide material properties between at least two states. The channel region can be electromagnetically influenced according to the states of the modulation material, especially when there is an electrical potential difference between the first gate electrode and the source/drain regions (SD1, SD2). The electrical conductivity of the channel region can be controlled via the states of the modulation material and/or via the state changes. The modulation region is made from an organic and/or inorganic material, especially in the form of a mono-layer.

公开(公告)号：DE10153561A1

公开(公告)日：2003-05-28

申请号：DE10153561

申请日：2001-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/792

Abstract: The cell has a charge-trapping gate configuration with each gate substantially independently storing the information. The storage of the information units and binary bits are done independent of each another in a memory cell (10). The charge tipping gate configurations are accessed by a source/drain configuration (SD1, SD2) and controlled by a control gate configuration. An Independent claim is also included for a method to fabricate a charge trapping memory cell.

公开(公告)号：FR2828759A1

公开(公告)日：2003-02-21

申请号：FR0210405

申请日：2002-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C11/56 ,  H01L29/788 ,  G11C11/34 ,  H01L29/792

Abstract: A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.

公开(公告)号：DE10131625A1

公开(公告)日：2003-01-23

申请号：DE10131625

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L27/105 ,  H01L21/02 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor storage device, in which a semiconductor substrate or similar, a passivation zone (21) and/or a surface zone (20a, 21a) are formed on it with a CMOS structure and in which in the region of the semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) on it are formed a capacitor arrangement (2) of capacitor devices (10-1...10-4) serving as storage elements. At least one part of the capacitor devices (10-1...10-4) are formed with a number of mutually-parallel connected discrete capacitors (C1,C2).

公开(公告)号：DE10105244A1

公开(公告)日：2002-08-22

申请号：DE10105244

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  ENDERS GERHARD

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/108

Abstract: The arrangement has first contact elements (11) arranged in a trench in an insulating material (15) essentially underneath and in electrical contact with lower electrode devices (14) to be contacted using a damascening technique. The first contact elements are isolated by intermediate regions (13) from adjacent condenser devices (10-3) that are not to be contacted. Independent claims are also included for the following: a semiconducting memory device.

公开(公告)号：DE10065664A1

公开(公告)日：2002-07-11

申请号：DE10065664

申请日：2000-12-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  KASTNER MARCUS J

IPC: H01L21/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12

Abstract: The memory device has on selection transistor (2,3) and one associated capacitor module (10,20) per memory cell. The capacitor modules of consecutive memory cells are arranged alternately on the front and rear (V,R) of a substrate wafer. The modules formed on the rear side of the substrate wafer are in an insulating layer formed in a recess in the rear side to protect the capacitors from the influence of subsequent processes.

公开(公告)号：DE102006003393A1

公开(公告)日：2007-04-12

申请号：DE102006003393

申请日：2006-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MUELLER TORSTEN ,  MIKOLAJICK THOMAS ,  WILLER JOSEF

IPC: H01L21/8247

Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

公开(公告)号：DE10131626B4

公开(公告)日：2006-07-27

申请号：DE10131626

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507