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公开(公告)号:DE10144462C1
公开(公告)日:2002-11-28
申请号:DE10144462
申请日:2001-09-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEUS HORST , AUBURGER ALBERT , PAULUS STEFAN , STADLER BERND
Abstract: Electronic component comprises a semiconductor chip (4) and a passive component (7). The chip is electrically connected to a wiring structure which is enclosed together with the passive component and the chip by a plastic housing (14). An Independent claim is also included for a process for the production of the electronic component. Preferred Features: The wiring structure is three-dimensional. The passive component is electrically connected to the chip using bonding wires (13). The passive component is connected to the chip using Flip-Chip technology. The passive component is an adjustable electrical resistor. An insulator (5) is arranged between the chip and passive component.
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公开(公告)号:DE102014111420B4
公开(公告)日:2022-03-17
申请号:DE102014111420
申请日:2014-08-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WACHTER ULRICH , HUBER VERONIKA , KILGER THOMAS , OTREMBA RALF , STADLER BERND , MAIER DOMINIC , SCHIESS KLAUS , SCHLOEGL ANDREAS , WAHL UWE
IPC: H01L21/50 , H01L21/283 , H01L21/768 , H01L23/28 , H01L23/36 , H01L23/485 , H01L33/48
Abstract: Verfahren zur Herstellung eines Halbleitergehäuses, wobei das Verfahren umfasst:Bereitstellen eines Halbleiter-Nacktchips mit einem Anschluss an einer ersten Seite des Nacktchips;Plattieren einer Kupferschicht an einer der ersten Seite gegenüberliegenden zweiten Seite des Nacktchips, wobei das Plattieren auf Wafer-Ebene erfolgt;Einbetten des Nacktchips in eine Formmasse, so dass der Nacktchip an allen Seiten, mit Ausnahme der ersten Seite, von der Formmasse bedeckt ist;Dünnen der Formmasse an einer zu der zweiten Seite des Nacktchips benachbarten Seite der Formmasse, um die Kupferschicht an der zweiten Seite des Nacktchips freizulegen, ohne dabei die zweite Seite des Nacktchips freizulegen; undAusbilden einer elektrischen Verbindung mit dem Anschluss an der ersten Seite des Nacktchips.
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公开(公告)号:DE10146854B4
公开(公告)日:2009-05-20
申请号:DE10146854
申请日:2001-09-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PAULUS STEFAN , AUBURGER ALBERT , THEUS HORST , STADLER BERND
Abstract: The electronic component (2) comprises the semiconductor chip (4) on a metal substrate (6), and a housing (12). There is also a screen (124) against HF electromagnetic radiation, as an integral part of the housing, forming at least one part of the housing wall (122).The screen may comprise a metal, or a non-conductor, or non-conductor with metal plating. The metal substrate may contain a wiring structure (8) round the semiconductor chip(s), whose contact faces (43) are conductively coupled by bonding wires (10) to contact pads (81) of wiring structure. Independent claims are included for mfg. method of the electronic component.
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公开(公告)号:DE10144464C2
公开(公告)日:2003-07-17
申请号:DE10144464
申请日:2001-09-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEUS HORST , AUBURGER ALBERT , PAULUS STEFAN , STADLER BERND
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公开(公告)号:DE10144467A1
公开(公告)日:2003-04-10
申请号:DE10144467
申请日:2001-09-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEUS HORST , AUBURGER ALBERT , PAULUS STEFAN , STADLER BERND
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公开(公告)号:DE10032369C2
公开(公告)日:2002-05-16
申请号:DE10032369
申请日:2000-07-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: GOTTSWINTER CHRISTIAN , NEUHOFF OSKAR , STADLER BERND
Abstract: The covering device covers a ceramic module with electronic components arranged between a ceramic substrate and an upper covering plate of the covering device. The covering device is spaced apart by spacers from the surface of the ceramic substrate fitted with components. The covering device is fixed on the ceramic module by snap-in elements which engage in lateral cutouts in the ceramic substrate.
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公开(公告)号:DE19700393C2
公开(公告)日:2002-03-14
申请号:DE19700393
申请日:1997-01-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor: JANCZEK THIES , STADLER BERND , HOUDEAU DETLEF
IPC: G01L9/04 , B81B7/00 , G01L9/00 , G01L19/14 , H01L23/02 , H01L23/04 , B81B3/00 , H01L25/16 , G01L7/08
Abstract: A housing for a semiconductor sensor configuration, in which a sensor and an evaluation logic are integrated in a semiconductor body is disclosed. The housing has a base body upon which the semiconductor body is applied and a cover that encloses the semiconductor body in the base body. The cover is directly set on the base body of the housing and contains a membrane and/or labyrinth.
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