公开(公告)号：JP2005175478A

公开(公告)日：2005-06-30

申请号：JP2004353482

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN XIANGDONG ,  CHIDAMBARRAO DURESETI ,  WANG GENG

IPC: H01L27/08 ,  H01L21/8238 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/745 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/783

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET which dynamically varies the threshold voltage on an SOI.
SOLUTION: When a body control contact is provided adjacent to a transistor and between the transistor and a contact to a substrate or a well in which the transistor is formed, the substrate of the transistor can be connected to and disconnected from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold, resulting in good performance maintained even at low supply voltages and reduced power consumption/dissipation, which are particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate is disconnected from a voltage source in the "on" state) are avoided because the substrate is discharged when the transistor is switched to the "off" state. The transistor configuration can be used with n-type and p-type transistors in the case of complementary pairs or the like.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在SOI上动态地改变阈值电压的MOSFET。 解决方案：当身体控制触点设置在晶体管附近以及晶体管与形成晶体管的衬底或阱的触点之间时，晶体管的衬底可以连接到零点 （接地）或基本上任意的低电压，根据施加到晶体管的栅极的控制信号，以使晶体管呈现可变阈值，导致即使在低电源电压下也保持良好的性能，并且降低功耗/耗散，这特别是 有利于便携式电子设备。 避免浮体效应（当晶体管基板从“导通”状态的电压源断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 在互补对等的情况下，晶体管配置可以与n型和p型晶体管一起使用。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2010245514A

公开(公告)日：2010-10-28

申请号：JP2010050893

申请日：2010-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  LIDIJA SEKARIC ,  LIU XIAO HU

IPC: H01L21/336 ,  B82B1/00 ,  B82B3/00 ,  H01L27/08 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7843 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor nanowire device for achieving a high on current for a high-performance complementary-metal oxide semiconductor (CMOS) circuit. SOLUTION: A semiconductor nanowire 32 having semiconductor pads 33A, 37A at both the ends is suspended over a substrate. While the semiconductor nanowire is being subjected to longitudinal stress by a stress-generating liner section, a gate dielectric 36 and a gate electrode 38 are formed on a middle section of the semiconductor nanowire. Since a strained state of the semiconductor nanowire is fixed by formation of the gate dielectric and the gate electrode, a middle section of the semiconductor nanowire is subjected to inherent longitudinal internal stress after removing the stress-generating liner. Source and drain regions 33B and 37B are formed in the semiconductor pads, thus obtaining a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于实现高性能互补金属氧化物半导体（CMOS）电路的高导通电流的半导体纳米线器件。 解决方案：在两个端部具有半导体焊盘33A，37A的半导体纳米线32悬置在衬底上。 当半导体纳米线被应力产生衬套部分施加纵向应力时，在半导体纳米线的中间部分上形成栅极电介质36和栅电极38。 由于通过形成栅极电介质和栅电极来固定半导体纳米线的应变状态，所以在除去应力产生衬垫之后，半导体纳米线的中间部分受到固有的纵向内应力。 源极和漏极区33B和37B形成在半导体焊盘中，从而获得半导体纳米线晶体管。 中间线（MOL）电介质层可以直接形成在源极和漏极焊盘上。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007123898A

公开(公告)日：2007-05-17

申请号：JP2006290998

申请日：2006-10-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  GREENE BRIAN J ,  KERN LIM

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/0653 ,  H01L29/7846

Abstract: PROBLEM TO BE SOLVED: To provide a structure for adding an effective stress without influencing the arrangement of an element separation region to improve characteristics of a field effect transistor having a channel region, a source region, and a drain region which are arranged in an active semiconductor region. SOLUTION: A buried dielectric stressor element 102 having a horizontally extending upper surface is arranged below one part of an active semiconductor region 104 separated by a trench separation region 106. This dielectric stressor consists of an oxide film by oxidation of a porous silicon, and generates a compression or extension stress based on the degree of porous formation. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于增加有效应力而不影响元件分离区域的布置的结构，以改善具有沟道区域，源极区域和漏极区域的场效应晶体管的特性，所述沟道区域，源极区域和漏极区域布置 在有源半导体区域。 解决方案：具有水平延伸的上表面的埋置介质应力元件102被布置在由沟槽分离区域106分隔开的有源半导体区域104的一部分的下面。该介电应力源由氧化膜由氧化多孔硅 ，并且基于多孔形成的程度产生压缩或延伸应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP2024995A4

公开(公告)日：2013-07-03

申请号：EP07797764

申请日：2007-05-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L21/76283

公开(公告)号：EP1910954A4

公开(公告)日：2012-04-11

申请号：EP06800366

申请日：2006-07-26

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

公开(公告)号：EP1997145A4

公开(公告)日：2011-07-06

申请号：EP07757883

申请日：2007-03-05

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7842

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP1856740A4

公开(公告)日：2009-02-25

申请号：EP06718261

申请日：2006-01-12

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/00

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

Abstract: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP1692717A4

公开(公告)日：2008-04-09

申请号：EP03819249

申请日：2003-12-08

Applicant: IBM

Inventor： BUEHRER FREDERICK WILLIAM ,  CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract translation: 施加在由半导体材料的结构或主体（例如衬底或层）限定的边界上的应力膜提供了在接近边界的半导体材料中从拉应力至压应力的变化，并且用于修改退火期间的硼扩散速率和 从而改变最终的硼浓度和/或分布/梯度。 在场效应晶体管的情况下，栅极结构可以形成为具有或不具有侧壁以相对于源极/漏极，延伸和/或晕圈注入来调节边界的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的降低。