公开(公告)号：EP1062849A4

公开(公告)日：2004-08-25

申请号：EP99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/0082 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551

Abstract: A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP1629509A4

公开(公告)日：2009-10-21

申请号：EP04775972

申请日：2004-05-11

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

IPC: H05K1/16 ,  H01C1/012 ,  H01C7/00 ,  H01C17/065 ,  H05K1/02 ,  H05K1/09 ,  H05K3/12

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

公开(公告)号：EP1695360A4

公开(公告)日：2009-06-03

申请号：EP04813997

申请日：2004-12-14

Applicant: MOTOROLA INC

Inventor： CROSWELL ROBERT T ,  DUNN GREGORY J ,  LEMPKOWSKI ROBERT B ,  TUNGARE AROON V ,  SAVIC JOVICA

IPC: H05K1/16 ,  H01G20060101 ,  H01G4/12 ,  H01G4/33 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

公开(公告)号：WO2007075714A3

公开(公告)日：2007-12-21

申请号：PCT/US2006048472

申请日：2006-12-19

Applicant: MOTOROLA INC ,  KEMET ELECTRONICS CORP ,  DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  LESSNER PHILIP M ,  PREVALLET MICHAEL D ,  PRYMAK JOHN D

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  LESSNER PHILIP M ,  PREVALLET MICHAEL D ,  PRYMAK JOHN D

IPC: H01G9/00

CPC classification number: H01G9/045 ,  H01G9/0032 ,  H01G9/055 ,  H01G9/15 ,  H05K1/162 ,  H05K3/383 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315

Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymer layer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

Abstract translation: 嵌入式电容器包括在第一铜层上包括第一铜层（205）和铝层（210）的双金属箔（500）。 铝层具有邻近第一铜层的平滑侧面和与第一铜层相对的高表面积纹理化侧面（215）。 双金属箔还包括在铝层的高表面积纹理化侧的氧化铝层（305），氧化铝层上的导电聚合物层（420）和覆盖氧化铝层的第二铜层（535） 。 双金属箔可以嵌入在电路板（700）中以形成高价值的嵌入式电容器。

公开(公告)号：WO2006130244A2

公开(公告)日：2006-12-07

申请号：PCT/US2006013995

申请日：2006-04-14

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CHELINI REMY J ,  DEAN TIMOTHY B

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  DEAN TIMOTHY B

CPC classification number: H05K3/025 ,  B32B7/06 ,  B32B9/00 ,  B32B9/041 ,  B32B15/00 ,  B32B15/043 ,  B32B15/20 ,  B32B2264/102 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/54 ,  B32B2307/546 ,  B32B2307/714 ,  B32B2457/08 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2203/0264 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract translation: 在一个实施例中，可剥离电路板箔（200）具有通过包括共沉积层（250）的无机高温释放结构（215）结合的金属支撑层（205）和导电金属箔层（210） 和金属氧化物层（260）。 共沉积层包含镍和硼，磷和铬中的一种或多种的混合物。 在第二实施例中，可剥离印刷电路箔（200）具有设置在金属箔层上的结晶化电介质氧化物层（405）和设置在结晶化电介质氧化物层上的电极层（415），形成介电剥离电路板箔 （400），其可以粘附到柔性或刚性电路板的层上，之后金属支撑层可以被剥离，留下包括金属箔层，结晶的电介质氧化物层和电极层的电容结构。

公开(公告)号：WO2006101638A2

公开(公告)日：2006-09-28

申请号：PCT/US2006005839

申请日：2006-02-17

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

Inventor： DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

IPC: B44C1/22 ,  C23F1/00

CPC classification number: C23F1/40 ,  C23F1/02 ,  C23F1/32 ,  C23F1/34 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/025 ,  H05K3/06 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0746

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

Abstract translation: 公开了一种用于制造图案化的嵌入式电容层的方法。 该方法包括制造覆盖在印刷电路衬底（505）上的导电金属层（515）上的陶瓷氧化物层（510），在区域（705）内穿孔（1320）陶瓷氧化物层，以及去除 （1325）通过化学蚀刻导电金属层的区域中的陶瓷氧化物层和导电金属层。 陶瓷氧化物层可以小于1微米厚。

公开(公告)号：WO0211500A2

公开(公告)日：2002-02-07

申请号：PCT/US0123238

申请日：2001-07-24

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J

IPC: H05K1/16 ,  H05K3/46 ,  H05K

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/49156 ,  Y10T29/49167

Abstract: A method is provided for forming an embedded, low profile capacitor in a multilayer printed circuit board. The method entails providing a first metal plate (16) on a dielectric substrate (14). A dielectric layer (18) of a photopolymeric material is applied onto a first region (17) of the first metal plate, surrounded by a second region (19) that is exposed. A second metal plate (24) is deposited onto the dielectric layer and the second region (19) of the first metal plate. The second plate (24) is then patterned to define an upper electrode (26) on the dielectric layer that is electrically isolated from the first metal plate. This may be accomplished by forming a trench (34) in the second metal plate above the dielectric layer. In one aspect, the resulting capacitor thus comprises a lower electrode structure (28) derived mainly from the first metal plate, a dielectric layer (20) overlying the first region of the first metal plate, and an upper electrode (26) overlying the dielectric layer. The lower metal structure also includes an extension (32) deposited onto the second region of the first metal layer about the dielectric layer and including a lip overlying a perimeter of the dielectric layer surface.

Abstract translation: 提供了一种用于在多层印刷电路板中形成嵌入式薄型电容器的方法。 该方法需要在电介质基片（14）上提供第一金属板（16）。 将光聚合材料的电介质层（18）施加到第一金属板的第一区域（17）上，被暴露的第二区域（19）围绕。 第二金属板（24）沉积在第一金属板的电介质层和第二区域（19）上。 然后将第二板（24）图案化以限定在与第一金属板电隔离的电介质层上的上电极（26）。 这可以通过在介电层上方的第二金属板中形成沟槽（34）来实现。 一方面，所得到的电容器包括主要由第一金属板衍生的下电极结构（28），覆盖在第一金属板的第一区域上的电介质层（20）和覆盖在电介质上的上电极 层。 下部金属结构还包括在电介质层周围沉积在第一金属层的第二区域上的延伸部（32），并且包括覆盖在电介质层表面的周边上的唇缘。

公开(公告)号：WO2009155204A4

公开(公告)日：2010-04-29

申请号：PCT/US2009047079

申请日：2009-06-11

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  BLAKE TERANCE B

Inventor： DUNN GREGORY J ,  BLAKE TERANCE B

IPC: G06T5/00 ,  H04N5/225

CPC classification number: H04N5/272 ,  G06T11/60 ,  H04M1/72544 ,  H04M2250/12 ,  H04M2250/52 ,  H04M2250/62 ,  H04N5/232 ,  H04N5/2621 ,  H04N2007/145

Abstract: A device and method of background substitution are disclosed. One or more cameras in a mobile device obtain a depth image. A processor in or external to the device segments the foreground from the background of the image. The original background is removed and a stored background image or video is substituted in place of the original background. The substituted background is altered dependent on the attitude and motion of the device, which is sensed by one or more sensors in the device. A portion of the stored background selected as the substitute background varies in correspondence with the device movement.

Abstract translation: 公开了背景替换的装置和方法。 移动设备中的一个或多个摄像头获取深度图像。 设备中或设备外部的处理器将前景从图像背景中分割出来。 原始背景将被删除，并且存储的背景图像或视频会替换原始背景。 取代的背景根据装置的姿态和运动而改变，装置的一个或多个传感器感测到该姿态和运动。 选择作为替代背景的一部分存储背景随着设备移动而变化。

公开(公告)号：WO2010027570A3

公开(公告)日：2010-04-22

申请号：PCT/US2009051386

申请日：2009-07-22

Applicant: MOTOROLA INC ,  DAI XUNHU ,  CROSWELL ROBERT ,  PETSINGER JEFFREY ,  SADLER DANIEL J ,  DUNN GREGORY J

Inventor： DAI XUNHU ,  CROSWELL ROBERT ,  PETSINGER JEFFREY ,  SADLER DANIEL J ,  DUNN GREGORY J

IPC: G06F3/041 ,  G06F3/01 ,  H03K17/96

CPC classification number: G06F3/016 ,  G06F3/0202 ,  H03K17/9622 ,  H03K2217/96062

Abstract: Touch sensors with one or more piezoelectric elements and devices containing such touch sensors are presented. The touch sensor contains keys that are independently actuated. Contact with a key provides tactile feedback through the piezoelectric element to the user. Each key provides an individual tactile feedback pattern that is dependent on the particular key contacted as well as the function of the key at the time of contact. Actuation of the key provides a different tactile feedback pattern. The piezoelectric element is bonded directly to a printed circuit board, on which electronic components are also mounted.

Abstract translation: 提供具有一个或多个压电元件的触摸传感器和包含这种触摸传感器的装置。 触摸传感器包含独立启动的按键。 与键的接触通过压电元件向使用者提供触觉反馈。 每个键提供一个独立的触觉反馈模式，这取决于所联系的特定键以及键的功能。 钥匙的启动提供了不同的触觉反馈模式。 压电元件直接结合到印刷电路板上，电子元件也安装在印刷电路板上。

公开(公告)号：WO2006101638B1

公开(公告)日：2007-02-15

申请号：PCT/US2006005839

申请日：2006-02-17

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

Inventor： DUNN GREGORY J ,  CROSWELL ROBERT T ,  MAGERA JAROSLAW A ,  SAVIC JOVICA ,  TUNGARE AROON V

IPC: H01L21/302

CPC classification number: C23F1/40 ,  C23F1/02 ,  C23F1/32 ,  C23F1/34 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/025 ,  H05K3/06 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0746

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

Abstract translation: 公开了一种制造图案化的嵌入式电容层的方法。 该方法包括制造（1305,1310）覆盖覆盖在印刷电路基板（505）上的导电金属层（515）的陶瓷氧化物层（510），在区域（705）内对陶瓷氧化物层进行穿孔（1320） （1325）通过导电金属层的化学蚀刻在该区域中的陶瓷氧化物层和导电金属层。 陶瓷氧化物层可以小于1微米厚。