公开(公告)号：HUE043517T2

公开(公告)日：2019-08-28

申请号：HUE11752672

申请日：2011-08-03

Applicant: QUALCOMM INC

Inventor： RAO HARI M ,  KIM JUNG PILL ,  KANG SEUNG H ,  ZHU XIAOCHUN ,  KIM TAE HYUN ,  LEE KANGHO ,  LI XIA ,  HSU WAH NAM ,  HAO WUYANG ,  SUH JUNGWON ,  YU NICHOLAS K ,  NOWAK MATTHEW MICHAEL ,  MILLENDORF STEVEN M ,  ASHKENAZI ASAF

IPC: G11C17/16 ,  G11C11/16 ,  G11C17/02

公开(公告)号：IN318MUN2013A

公开(公告)日：2015-05-29

申请号：IN318MUN2013

申请日：2013-02-18

Applicant: QUALCOMM INC

Inventor： RAO HARI M ,  KIM JUNG PILL ,  KANG SEUNG H ,  ZHU XIAOCHUN ,  KIM TAE HYUN ,  LEE KANGHO ,  LI XIA ,  HSU WAH NAM ,  HAO WUYANG ,  SUH JUNGWON ,  YU NICHOLAS K ,  NOWAK MATTHEW MICHAEL ,  MILLENDORF STEVEN M ,  ASHKENAZI ASAF

IPC: G11C17/16 ,  G11C11/16 ,  G11C17/02

Abstract: A method of generating a non reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device (102) includes a bitcell having a first MTJ (106) and a second MTJ (108) and programming circitry (104) configured to generate a non reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

公开(公告)号：CA2807392A1

公开(公告)日：2012-02-09

申请号：CA2807392

申请日：2011-08-03

Applicant: QUALCOMM INC

Inventor： RAO HARI M ,  KIM JUNG PILL ,  KANG SEUNG H ,  ZHU XIAOCHUN ,  KIM TAE HYUN ,  LEE KANGHO ,  LI XIA ,  HSU WAH NAM ,  HAO WUYANG ,  SUH JUNGWON ,  YU NICHOLAS K ,  NOWAK MATTHEW MICHAEL ,  MILLENDORF STEVEN M ,  ASHKENAZI ASAF

IPC: G11C17/16 ,  G11C11/16 ,  G11C17/02

Abstract: A method of generating a non - reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device (102) includes a bitcell having a first MTJ (106) and a second MTJ (108) and programming circitry (104) configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

公开(公告)号：ES2322792T3

公开(公告)日：2009-06-29

申请号：ES00980283

申请日：2000-11-03

Applicant: QUALCOMM INC

Inventor： YU NICHOLAS K ,  EASTON KENNETH D ,  SANKURATRI RAGHU

IPC: H04W52/02 ,  H03L7/00 ,  H04B1/02 ,  H04B1/16 ,  H04B7/26 ,  H04M1/73

Abstract: Un dispositivo (100) para activar un reloj (102) de modo activo después de un periodo de reposo para su uso en una estación móvil en el que componentes seleccionados de la estación móvil operan usando un reloj (104) de modo de reposo durante el periodo de reposo y un reloj (102) de modo activo más rápido durante periodos que no son de reposo comprendiendo dicho dispositivo: medios para estimar (108) un tiempo de reactivación usando el reloj (104) de modo de reposo; medios para compensar errores en el tiempo de reactivación estimado provocados por diferencias de precisión entre el reloj (104) de modo de reposo y el reloj (102) de modo activo; y medios para activar (114) el reloj (102) de modo activo en el tiempo de reactivación compensado; en el que los medios para compensar están configurados para usar un reloj (106) de modo de transición, que se emplea tanto al comienzo como al final de cada periodo de reposo, para compensar dichos errores, en el que dicho reloj (106) de modo de transición tiene una frecuencia sustancialmente mayor que la del reloj de modo de reposo.

公开(公告)号：DE60042080D1

公开(公告)日：2009-06-04

申请号：DE60042080

申请日：2000-11-03

Applicant: QUALCOMM INC

Inventor： YU NICHOLAS K ,  EASTON KENNETH D ,  SANKURATRI RAGHU

IPC: H04W52/02 ,  H03L7/00 ,  H04B1/02 ,  H04B1/16 ,  H04B7/26 ,  H04M1/73

公开(公告)号：HK1063674A1

公开(公告)日：2005-01-07

申请号：HK04106447

申请日：2004-08-27

Applicant: QUALCOMM INC

Inventor： KHAN SAFI ,  YU NICHOLAS K ,  HASQUINE DAVID W ,  FUCHS ROBERT ,  STAFFORD DAVID ,  DHAWAN RAJAT

IPC: G06F20060101 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38

公开(公告)号：AU776533B2

公开(公告)日：2004-09-16

申请号：AU1756701

申请日：2000-11-03

Applicant: QUALCOMM INC

Inventor： YU NICHOLAS K ,  EASTON KENNETH D ,  SANKURATRI RAGHU

IPC: H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04M1/73 ,  H04W52/02 ,  H04Q7/00

公开(公告)号：BR0015247A

公开(公告)日：2002-12-31

申请号：BR0015247

申请日：2000-11-03

Applicant: QUALCOMM INC

Inventor： YU NICHOLAS K ,  EASTON KENNETH D ,  SANKURATRI RAGHU

IPC: H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04M1/73 ,  H04W52/02 ,  H04Q7/00

公开(公告)号：HK1040872A1

公开(公告)日：2002-06-21

申请号：HK02102349

申请日：2002-03-27

Applicant: QUALCOMM INC

Inventor： BUTLER BRIAN K ,  YU NICHOLAS K ,  EASTON KENNETH D

IPC: G06F1/08 ,  G06F1/32 ,  H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04L7/02 ,  H04L7/033 ,  H04W52/02 ,  H04Q ,  H04B ,  G06F

Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

公开(公告)号：CA2704892A1

公开(公告)日：2001-06-21

申请号：CA2704892

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.