公开(公告)号：FR2928029A1

公开(公告)日：2009-08-28

申请号：FR0851266

申请日：2008-02-27

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

Inventor： BERNARD EMILIE ,  GUILLAUMOT BERNARD ,  CORONEL PHILIPPE

IPC: H01L21/336 ,  H01L29/78

Abstract: L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comportant une région semi-conductrice de canal et une région de grille, la région de grille comprenant au moins une partie enterrée s'étendant sous la région de canal. La formation de la partie enterrée de la région de grille comprend :- une formation d'une cavité sous la région de canal,- un remplissage au moins partiel de la cavité par au moins du silicium et un métal,- la formation d'un siliciure dudit métal.

公开(公告)号：FR2860099B1

公开(公告)日：2006-01-06

申请号：FR0310984

申请日：2003-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  HARTMANN JOEL

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2853454B1

公开(公告)日：2005-07-15

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.

公开(公告)号：FR2848724B1

公开(公告)日：2005-04-15

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2860099A1

公开(公告)日：2005-03-25

申请号：FR0310984

申请日：2003-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  HARTMANN JOEL

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/11

Abstract: The method involves forming a temporary monocrystalline material portion over a surface (S) of a conducting substrate (100). A semiconductor material (2) is deposited on the portion of temporary material. A part of the temporary material is withdrawn via an access zone. An insulating coating is formed on parts of the material (2). A conducting material (4) is formed above and below a central part of the material (2). An independent claim is also included for a random access memory unit.

公开(公告)号：FR2833106B1

公开(公告)日：2005-02-25

申请号：FR0115594

申请日：2001-12-03

Applicant: ST MICROELECTRONICS SA

Inventor： FARCY ALEXIS ,  CORONEL PHILIPPE ,  ANCEY PASCAL ,  TORRES JOAQUIM

IPC: B81B7/00 ,  B81C3/00 ,  H01L21/50 ,  H01L21/56 ,  B81C1/00

Abstract: The circuit includes a first semiconductor substrate supporting the electronic circuit, and a second substrate carrying an electromechanical component. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component. The first phase of manufacture includes forming the semiconductor chip (PC) within a first substrate, and forming a cavity in the upper surface of this substrate to accommodate an auxiliary component. A wall remains around the cavity, leaving the cavity as a well. The second phase includes formation of the auxiliary component (CAX) on a second semiconductor substrate (SB2), separate from the first. The second substrate is then turned over and applied to the first substrate as a lid with the auxiliary component hanging within the cavity of the first substrate. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component.

公开(公告)号：FR2858876A1

公开(公告)日：2005-02-18

申请号：FR0350425

申请日：2003-08-12

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CORONEL PHILIPPE ,  LAPLANCHE YVES ,  PAIN LAURENT

IPC: G03F7/11 ,  G03F7/20 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/76

公开(公告)号：FR2852441A1

公开(公告)日：2004-09-17

申请号：FR0303194

申请日：2003-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MAZOYER PASCALE ,  SKOTNICKI THOMAS

IPC: G11C7/00 ,  G11C11/34 ,  G11C13/00 ,  H01L21/18 ,  H01L27/10 ,  H01L27/105

Abstract: The memory device has a memory cell (CM) with a membrane (MB) fixed on a substrate (SB). A deformable part (PDF) is situated at a distance to the substrate and is deformable between two stable mechanical positions corresponding to two logic levels of the memory cell. A deformation unit (MDF) is deforms the membrane. A detection unit (MDT) detects the logic level of the memory cell. Independent claims are also included for the following: (a) an integrated circuit (b) a method of controlling a logic level of a memory cell.

公开(公告)号：FR2826507B1

公开(公告)日：2004-07-02

申请号：FR0108192

申请日：2001-06-21

Applicant: ST MICROELECTRONICS SA

Inventor： FERREIRA PAUL ,  CORONEL PHILIPPE

IPC: H01L21/033 ,  H01L21/266 ,  H01L21/301 ,  H01L21/8238

公开(公告)号：FR2918795B1

公开(公告)日：2009-10-02

申请号：FR0756447

申请日：2007-07-12

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  BELREDON XAVIER

IPC: H01L27/146 ,  H01L31/02 ,  H01L31/18