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公开(公告)号：KR1020050098601A
公开(公告)日：2005-10-12
申请号：KR1020040024024
申请日：2004-04-08
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L24/50 , H01L24/86 , H01L25/072 , H01L2224/0405
Abstract: 본 발명의 탭 패키지용 반도체칩은, 탭 패키지 제조를 위하여 필름상에 탭 실장되는 탭 패키지용 반도체칩이다. 이 탭 패키지용 반도체칩은, 필름에 부착되는 제1 면 및 반대되는 제2 면을 갖는 칩 본체와, 칩 본체의 제1 면에서 상부, 하부 및 측부에 각각 배치되는 복수개의 칩 패드들을 구비한다. 칩 본체는 중심부분에 배치되는 중심영역을 기준으로 양 방향으로 가장자리에 이르기까지 구별되는 복수개의 영역들을 가지며, 칩 패드들 중 인접한 칩 패드들 사이의 간격은 복수개의 영역들에서 서로 다르다. 이에 따르면 실장공정 중에 가해지는 열로 인한 열변형 현상이 발생하더라도 반도체칩의 칩패드와 필름의 패드 사이의 오정렬이 발생하는 것을 억제시킬 수 있다.
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公开(公告)号：KR100505665B1
公开(公告)日：2005-08-03
申请号：KR1020030002417
申请日：2003-01-14
Applicant: 삼성전자주식회사
Inventor： 정예정
IPC: H01L21/66
CPC classification number: H01L22/32 , H01L23/49572 , H01L2224/16 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H05K1/0268 , H05K1/0393 , H05K2201/0949 , H05K2203/1545
Abstract: 테스트용 패드의 형상 통일화로 프로브 카드 호환성을 확대하고, 테스트용 패드의 간격을 넓혀 전기적 검사시 정확성을 개선하고, 테이프 패키지의 전체 길이를 축소시킬 수 있는 테스트용 패드가 이면에 형성된 테이프 패키지에 관해 개시한다. 이를 위해 본 발명은 상면에 있는 테스트용 패드를 베이스 필름의 관통홀을 통해 베이스 필름의 이면으로 배치한다.
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公开(公告)号：KR1020050023930A
公开(公告)日：2005-03-10
申请号：KR1020030061498
申请日：2003-09-03
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H05K1/112 , H05K3/361 , H01L2224/05599
Abstract: PURPOSE: A TAB(Tape Automated Bonding) tape and a TCP(Tape Carrier Package) using the same are provided to realize fine pitch in a semiconductor device by improving the structure of the TAB tape. CONSTITUTION: A TAB tape includes a base film, a fist metal line pattern, and a second metal line pattern. The base film(330) is made of an insulating substance. A via hole(360) is formed at a predetermined portion of the base film. The first metal line pattern(320) is formed on a first surface of the base film. The second metal line pattern(340) is formed on a second surface of the base film. The second metal line is electrically connected with a terminal of the first surface of the base film through a conductive material of the via hole. The first and second metal line patterns are overlapped with each other.
Abstract translation: 目的：通过改进TAB带的结构，提供一种TAB（磁带自动接合）带和使用该带的TCP（磁带载体封装）以实现半导体器件的精细间距。 构成：TAB带包括基膜，第一金属线图案和第二金属线图案。 基膜（330）由绝缘物质制成。 在基膜的预定部分处形成通孔（360）。 第一金属线图案（320）形成在基膜的第一表面上。 第二金属线图案（340）形成在基膜的第二表面上。 第二金属线通过通孔的导电材料与基膜的第一表面的端子电连接。 第一和第二金属线图案彼此重叠。
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公开(公告)号：KR1020050015422A
公开(公告)日：2005-02-21
申请号：KR1020030054221
申请日：2003-08-05
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/13452 , H01L23/5387 , H01L2224/16 , H01L2924/07811 , H05K1/118 , H05K1/147 , H05K2201/068 , H05K2201/10681 , H01L2924/00
Abstract: PURPOSE: An inexpensive flexible film package module and a method for manufacturing the flexible film package module are provided to reduce the manufacturing cost of a flexible film package and produce a small LCD(Liquid Crystal Display) by connecting a cheap FPC(Flexible Printed Circuit) insulating substrate and a polyimide substrate and using the connected substrate as a tape film. CONSTITUTION: An inexpensive flexible film package module includes a plurality of semiconductor packages(100') and an inexpensive input terminal connector(150). Each semiconductor package includes the first insulating substrate made of polyimide, a chip paddle formed on the first insulating substrate, a semiconductor chip mounted on the chip paddle, an input circuit pattern formed on the first insulating substrate to connect a circuit pattern in the chip paddle to a printed circuit board, and an output circuit pattern formed on the first insulating substrate to connect the circuit pattern in the chip paddle to a glass panel(300). The input terminal connector is connected to the input circuit pattern and includes the second insulating substrate made of a material cheaper than the first insulating substrate and a common input circuit pattern formed on the second insulating substrate, electrically connected to the input circuit patterns of the semiconductor packages and finally connected to the printed circuit board.
Abstract translation: 目的：提供一种廉价的柔性膜封装模块和制造柔性膜封装模块的方法，以通过连接便宜的FPC（柔性印刷电路）来降低柔性膜封装的制造成本并生产小型LCD（液晶显示器） 绝缘基板和聚酰亚胺基板，并且使用连接的基板作为带膜。 构成：廉价的柔性膜封装模块包括多个半导体封装（100'）和便宜的输入端子连接器（150）。 每个半导体封装包括由聚酰亚胺制成的第一绝缘基板，形成在第一绝缘基板上的芯片焊盘，安装在芯片焊盘上的半导体芯片，形成在第一绝缘基板上的输入电路图案，以连接芯片焊盘中的电路图案 印刷电路板和形成在第一绝缘基板上的输出电路图案，以将芯片桨叶中的电路图案连接到玻璃面板（300）。 输入端子连接器连接到输入电路图案，并且包括由比第一绝缘基板便宜的材料制成的第二绝缘基板和形成在第二绝缘基板上的公共输入电路图案，电连接到半导体的输入电路图案 封装，最后连接到印刷电路板。
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公开(公告)号：KR1020040010101A
公开(公告)日：2004-01-31
申请号：KR1020030031400
申请日：2003-05-17
Applicant: 삼성전자주식회사
IPC: H01L21/60
Abstract: PURPOSE: A semiconductor package film having a reinforcement film and a fabricating method thereof are provided to enhance the tensile force by using the reinforcement film of synthetic resin instead of a reinforced metal pattern. CONSTITUTION: A semiconductor package film having a reinforcement film includes a base film(200) and a reinforcement film(243). The base film(200) is formed with a main area(210) and a marginal area(220). A plurality of circuit lines(254) are formed on the main area(210). The marginal area(220) is formed at both sides of the width direction of the main area(210). The first sprocket holes(222) are formed on the marginal area(220). The reinforcement film(243) is adhered on the marginal area(220) of one side of a top side and a bottom side of the base film(200).
Abstract translation: 目的：提供一种具有加强膜的半导体封装膜及其制造方法，以通过使用合成树脂的增强膜代替加强金属图案来增强张力。 构成：具有加强膜的半导体封装膜包括基膜（200）和增强膜（243）。 基膜（200）形成有主区域（210）和边缘区域（220）。 多个电路线路（254）形成在主区域（210）上。 边缘区域（220）形成在主区域（210）的宽度方向的两侧。 第一链轮孔（222）形成在边缘区域（220）上。 加强膜（243）粘附在基膜（200）的顶侧和底侧的一侧的边缘区域（220）上。
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Patent Agency Ranking
公开(公告)号：KR1020020076764A
公开(公告)日：2002-10-11
申请号：KR1020010016871
申请日：2001-03-30
Applicant: 삼성전자주식회사
IPC: H01L23/544
CPC classification number: H05K1/0268 , G01R31/2818 , G09G3/006 , H01L22/20 , H01L22/32 , H01L23/5387 , H01L2924/0002 , H01L2924/014 , H05K1/0293 , H05K1/11 , H05K1/189 , H05K2201/0305 , H05K2201/09381 , H05K2203/173 , H01L2924/00
Abstract: PURPOSE: A chip on film package having a test pad for evaluating an electric characteristic and a method for forming the same are provided to test terminals not applied to the outside by forming a test pad inside the chip on film package including manual devices. CONSTITUTION: A chip on film package(10) is formed with an LCD driver chip(100), a signal line(170), the first and the second test pad(110,120), the first, the second, and the third manual device portion(140,150,160), and a signal input portion(130). The signal input portion(130) receives data and control signals from an external control circuit and transfers the received data and control signals to the LCD driver chip(100) through the signal line(170). The first manual device portion(140) is used for stabilizing each voltage(V0 to V4). The second manual device portion(150) includes resistances(R1,R2) for controlling a voltage of VO. The third manual device portion(160) is formed by capacitors(C2) for boosting the voltage. The first and the second test pad(110,120) are used for testing terminals which are not applied to the outside through the signal input portion(130).
Abstract translation: 目的：通过在包括手动装置的胶片包装上的芯片内部形成测试垫，来提供具有用于评估电特性的测试焊盘和其形成方法的薄膜封装芯片，以测试不施加到外部的端子。 构成：薄膜封装（10）上的芯片形成有LCD驱动器芯片（100），信号线（170），第一和第二测试垫（110,120），第一，第二和第三手动装置 部分（140,150,160）和信号输入部分（130）。 信号输入部分（130）从外部控制电路接收数据和控制信号，并通过信号线（170）将接收的数据和控制信号传送到LCD驱动器芯片（100）。 第一手动装置部分（140）用于稳定每个电压（V0至V4）。 第二手动装置部分（150）包括用于控制VO电压的电阻（R1，R2）。 第三手动装置部分（160）由用于升压电压的电容器（C2）形成。 第一和第二测试焊盘（110,120）用于测试通过信号输入部分（130）未被施加到外部的端子。
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公开(公告)号：KR101700701B1
公开(公告)日：2017-02-14
申请号：KR1020100092857
申请日：2010-09-24
Applicant: 삼성전자주식회사
IPC: G02F1/1345 , H05K1/18 , G02F1/1343 , G02F1/1362 , G02F1/133 , G09G3/36
CPC classification number: H01L27/1244 , G02F1/13452 , G09G3/20 , G09G2300/0426 , G09G2310/08 , G09G2330/021 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/105 , H01L2224/13124 , H01L2224/13639 , H01L2224/16225 , H01L2224/73204 , H01L2924/1426 , H05K1/148
Abstract: 화상표시장치는게이트및 소스구동신호들을제공하는반도체칩을포함하는인쇄회로기판과, 제1 단부가인쇄회로기판과접합됨과아울러전기적으로연결되며, 반도체칩으로부터게이트및 소스구동신호들을수신하는플렉시블인쇄회로기판과, 플렉시블인쇄회로기판의제2 단부와전기적으로연결되고, 일측단부를따라연장되는게이트구동신호전달패턴, 일측단부와인접한타측단부를따라연장되는소스구동신호전달패턴및 복수의화소들을포함하는화상표시패널과, 게이트구동신호전달패턴을통하여게이트구동신호를수신하여복수의화소들의게이트라인들에제공하는적어도하나의게이트구동 IC 패키지, 및소스구동신호전달패턴을통하여소스구동신호를수신하여복수의화소들의소스라인들에제공하는적어도하나의소스구동 IC 패키지를포함한다. 소스구동 IC 패키지는, 화상표시패널에직접적으로접합되고, 유연성을가지는절연재질을포함하고, 인쇄회로기판에접합되지않는베이스기판과, 베이스기판상에실장되어소스구동신호를수신하여제공하는소스구동 IC, 소스구동 IC와전기적으로연결되어소스구동신호를수신하는소스구동신호입력패턴과, 및소스구동 IC와전기적으로연결되어복수의화소들의소스라인들에소스구동신호를제공하는소스구동신호출력패턴을포함한다.
Abstract translation: 根据示例性实施例，图像显示面板组件包括柔性印刷电路（FPC），图像显示面板，至少一个栅极驱动器集成电路（IC）封装以及至少一个源极驱动器IC封装。 FPC被配置为接收门和源驱动信号。 图像显示面板电连接到FPC，并且包括沿着图像显示面板的第一边缘的栅极驱动信号传递图案，沿着与第一端相邻的第二边缘的源极驱动信号传递图案，以及多个像素 。 所述至少一个栅极驱动器集成电路（IC）封装经配置以通过栅极驱动信号传输图案接收栅极驱动信号，并且被配置为向多个像素的栅极线提供栅极驱动信号。 所述至少一个源极驱动器IC封装经配置以通过所述源极驱动信号传输图案接收所述源极驱动信号，并且被配置为将所述源极驱动信号提供给所述多个像素的源极线。
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公开(公告)号：KR1020120077877A
公开(公告)日：2012-07-10
申请号：KR1020100139993
申请日：2010-12-31
Applicant: 삼성전자주식회사
IPC: H01L23/495 , H01L23/00 , H01L25/065 , H01L23/48
CPC classification number: H01L23/49531 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05553 , H01L2224/05554 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2224/48247 , H01L2224/4903 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L23/481
Abstract: PURPOSE: A semiconductor package is provided to reduce a semiconductor package by shortening an electrical transmission path between a lead frame and a semiconductor chip. CONSTITUTION: A semiconductor chip is mounted on a die pad. A lead frame is electrically connected to the semiconductor chip. A flexible film substrate(120) includes a metal wire(126). The semiconductor chip is electrically connected to a film substrate through a first substrate pad(122) connected to the semiconductor chip and the metal wire. The film substrate is electrically connected to the lead frame through a second substrate pad(124) connected to the metal wire and the lead frame.
Abstract translation: 目的：提供半导体封装以通过缩短引线框和半导体芯片之间的电传输路径来减少半导体封装。 构成：半导体芯片安装在管芯焊盘上。 引线框架电连接到半导体芯片。 柔性薄膜基板（120）包括金属线（126）。 半导体芯片通过连接到半导体芯片和金属线的第一基板焊盘（122）电连接到薄膜基板。 薄膜基板通过连接到金属线和引线框架的第二基板焊盘（124）电连接到引线框架。
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公开(公告)号：KR1020120009702A
公开(公告)日：2012-02-02
申请号：KR1020100070077
申请日：2010-07-20
Applicant: 삼성전자주식회사
IPC: H01L23/12 , H05K1/02 , H01L23/525
CPC classification number: H01L23/4985 , H01L23/49811 , H01L23/49838 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a film circuit board and a method for manufacturing a chip package are provided to improve the reliability of a device by cutting a film circuit board with a relatively small cut surface. CONSTITUTION: A base film(320) includes a chip mount area and an isolation area. The isolation area is divided into two chip mount areas and includes a cut area(A) and a non-cut area(B). A preliminary wire pattern with a first height is formed on the base film. A wire pattern(341) with a second height is formed in the cut area by selectively etching the preliminary wire pattern of the cut area.
Abstract translation: 目的：提供一种薄膜电路板的制造方法和芯片封装的制造方法，通过切割具有较小切割面的薄膜电路板来提高器件的可靠性。 构成：基膜（320）包括芯片安装区域和隔离区域。 隔离区分为两个芯片安装区域，包括切割区域（A）和非切割区域（B）。 在基膜上形成具有第一高度的初始线图案。 通过选择性地蚀刻切割区域的预备线图案，在切割区域中形成具有第二高度的线图案（341）。
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公开(公告)号：KR1020100021899A
公开(公告)日：2010-02-26
申请号：KR1020080080559
申请日：2008-08-18
Applicant: 삼성전자주식회사
CPC classification number: H05K1/0216 , H01L23/4985 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H05K1/114 , H05K1/189 , H05K2201/093 , H05K2201/09318 , H05K2201/09663 , H05K2201/09772 , H05K2201/09781 , H05K2201/10674 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: PURPOSE: A tape wiring substrate, a chip-on-film package, and a device assembly are provided to reduce a size and a weight of an electronic product and implement high integration. CONSTITUTION: A tape wiring substrate includes an insulation film substrate(10), a first metal pattern layer(20A), a second metal pattern layer(30A). The insulation film substrate includes a first main surface(11) and a second main surface(12) with one chip mounting region. One via or more are included between the first main surface and the second main surface. The plurality of first metal pattern layers are provided on the first main surface. The plurality of metal pattern layers are provided on the second main surface. The plurality of second metal pattern layers are provided on the second main surface and are electrically connected to the first pattern layer through a via.
Abstract translation: 目的：提供胶带布线基板，胶片封装和装置组件，以减小电子产品的尺寸和重量并实现高集成度。 构成：带状布线基板包括绝缘膜基板（10），第一金属图案层（20A），第二金属图案层（30A）。 绝缘膜基板包括具有一个芯片安装区域的第一主表面（11）和第二主表面（12）。 在第一主表面和第二主表面之间包括一个或多个通孔。 多个第一金属图案层设置在第一主表面上。 多个金属图案层设置在第二主表面上。 多个第二金属图案层设置在第二主表面上，并且通过通孔与第一图案层电连接。
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