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公开(公告)号：KR1020090105621A
公开(公告)日：2009-10-07
申请号：KR1020080031185
申请日：2008-04-03
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: PURPOSE: A method for cleaning a wafer and a device for performing the same are provided to remove the contaminant on the wafer by applying the ultrasound wave to the front surface of the wafer. CONSTITUTION: A wafer is immersed in a cleaning solution. An interval between the position for applying a first ultrasound wave and a first surface of the wafer is controlled(ST202). The first surface of the wafer is cleaned by applying the first ultrasound wave to the first surface of the wafer(ST204). The interval between the position for applying a second ultrasound wave and a second surface of the wafer are controlled(ST206). The second surface of the wafer is cleaned by applying the second ultrasound wave to the second surface of the wafer(ST208).
Abstract translation: 目的：提供清洁晶片的方法和用于执行晶片的装置，以通过将超声波施加到晶片的前表面来去除晶片上的污染物。 构成：将晶片浸入清洁溶液中。 控制用于施加第一超声波的位置与晶片的第一表面之间的间隔（ST202）。 通过将第一超声波施加到晶片的第一表面来清洁晶片的第一表面（ST204）。 控制用于施加第二超声波的位置与晶片的第二表面之间的间隔（ST206）。 通过将第二超声波施加到晶片的第二表面来清洁晶片的第二表面（ST208）。
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公开(公告)号：KR1020090001377A
公开(公告)日：2009-01-08
申请号：KR1020070065704
申请日：2007-06-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/76229 , H01L21/28141 , H01L21/31144 , H01L27/11521
Abstract: The method for forming the semiconductor device is provided to form the trench having the excellent lateral profile by etching the substrate using the aluminum oxide film pattern and the mask pattern as the etching mask. The insulating layer, the conductive film, and the aluminum oxide film and the mask are successively formed on the substrate(100). The aluminum oxide film is etched by using the mask as the etching mask. The preliminary aluminum oxide film pattern(128) is formed to expose the conductive film's surface in the first width. The side of the preliminary aluminum oxide film pattern is etched. The aluminum oxide film pattern is formed, exposing the conductive film surface in the second width which is broader than the first width. The conductive layer pattern(142), and the insulating layer pattern(144) and trench(148) are formed by using the mask and aluminum oxide film pattern as the etching mask.
Abstract translation: 提供了形成半导体器件的方法，通过使用氧化铝膜图案和掩模图案作为蚀刻掩模通过蚀刻衬底来形成具有优异横向轮廓的沟槽。 绝缘层，导电膜和氧化铝膜和掩模依次形成在基板（100）上。 通过使用掩模作为蚀刻掩模来蚀刻氧化铝膜。 形成初步氧化铝膜图案（128）以使第一宽度的导电膜的表面露出。 蚀刻初步氧化铝膜图案的一侧。 形成氧化铝膜图案，使导电膜表面暴露于比第一宽度宽的第二宽度。 通过使用掩模和氧化铝膜图案作为蚀刻掩模来形成导电层图案（142）和绝缘层图案（144）和沟槽（148）。
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公开(公告)号：KR1020080062186A
公开(公告)日：2008-07-03
申请号：KR1020060137655
申请日：2006-12-29
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: A method of drying a semiconductor substrate is provided to prevent a water mark from being formed on a surface of the substrate by substituting deionized water by isopropyl alcohol. An isopropyl alcohol solution is heated by a drying temperature to generate isopropyl alcohol vapor, and then a drying atmosphere having isopropyl alcohol vapor of 0.02 to 0.1 volume% is formed. A semiconductor substrate(200) is provided under the drying atmosphere while the drying temperature is maintained. The drying temperature is 120 to 150 °C, and the semiconductor substrate is provided at a speed of 1 to 6 mm/s. Deionized water is substituted by isopropyl alcohol on the semiconductor substrate.
Abstract translation: 提供一种干燥半导体衬底的方法，以通过用异丙醇代替去离子水来防止在衬底的表面上形成水痕。 异丙醇溶液在干燥温度下加热，生成异丙醇蒸气，形成异丙醇蒸气0.02〜0.1体积％的干燥气氛。 在干燥气氛下设置半导体基板（200），同时保持干燥温度。 干燥温度为120〜150℃，以1〜6mm / s的速度设置半导体基板。 去离子水由半导体衬底上的异丙醇代替。
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公开(公告)号：KR100829605B1
公开(公告)日：2008-05-15
申请号：KR1020060043035
申请日：2006-05-12
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L21/76229 , H01L27/11568
Abstract: SONOS 타입의 비휘발성 메모리 장치의 제조 방법에 관한 것으로서, 상기 기판으로부터 돌출되는 소자 분리막을 형성한다. 상기 소자 분리막에 의해 노출되는 상기 기판 상에 그 표면이 상기 소자 분리막의 표면 아래에 위치하는 제1 박막을 형성한다. 상기 제1 박막 상에만 질화물의 제2 박막 패턴을 형성한다. 상기 제2 박막 패턴과 소자 분리막 상에 제3 박막 및 제4 박막을 형성한다. 상기 제4 박막, 제3 박막, 제2 박막 패턴 및 제1 박막을 순차적으로 패터닝함으로써 상기 기판 상에 상기 제1 박막의 터널 절연막, 상기 제2 박막 패턴의 전하 트랩막, 상기 제3 박막의 블로킹 절연막 및 상기 제4 박막의 게이트 전극을 포함하는 구조물들을 형성한다. 그 결과 우수한 전기적 성능의 구현이 가능한 SONOS 타입의 비휘발성 메모리 장치가 완성된다.
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公开(公告)号：KR1020080006861A
公开(公告)日：2008-01-17
申请号：KR1020060066143
申请日：2006-07-14
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: A method for drying a semiconductor substrate and an apparatus for performing the same are provided to prevent the leaning effect of a capacitor caused by surface tension of water in a Marangoni dryer. A dipping process is performed to dip a semiconductor substrate into a receptacle with alcohol of a liquid state(S100). A moisture removal process is performed to remove moisture from the semiconductor substrate by removing relatively the alcohol with respect to the substrate dipped into the alcohol of the receptacle(S110). An alcohol removal process is performed to remove the remaining alcohol by dipping the substrate into an organic solvent including fluorine(S120). The alcohol includes isopropyl alcohol.
Abstract translation: 提供干燥半导体基板的方法及其执行装置，以防止Marangoni干燥器中由水的表面张力引起的电容器的倾斜效应。 进行浸渍处理以将半导体衬底浸入具有液态醇的容器中（S100）。 通过相对于浸入容器的醇中的基材去除相对于醇的水分，从而从半导体衬底去除水分（S110）。 通过将基材浸渍到包含氟的有机溶剂中来进行醇去除过程以除去剩余的醇（S120）。 酒精包括异丙醇。
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Patent Agency Ranking
公开(公告)号：KR1020070109694A
公开(公告)日：2007-11-15
申请号：KR1020060043035
申请日：2006-05-12
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L21/76229 , H01L27/11568 , H01L21/28282
Abstract: A method for manufacturing a SONOS(Silicon Oxide Nitride Oxide Semiconductor) type non-volatile memory device is provided to prevent plasma-etching damage and to improve charge trap characteristics by using a silicon nitride layer having a charge trap layer pattern. A trench is formed on a substrate(100). The trench is buried sufficiently and an isolation layer(108) is formed on the substrate. A first thin film including an insulating material is formed on the substrate which is exposed by the isolation layer. A second thin film pattern including silicon nitride is formed on the first thin film. A third thin film as a dielectric layer is formed on the resultant structure including the second thin film pattern and the isolation layer. A fourth thin film including a conductive material is formed on the third thin film. A gate structure(150) including a tunnel insulating layer pattern of the first thin film, a charge trap layer pattern of the second thin film pattern, a blocking insulating layer pattern of the third thin film, and a gate electrode of the fourth thin film is formed by patterning the four thin film, the third thin film, the second thin film pattern, and the first thin film. A source/drain(130) is formed under the surface of the substrate adjacent to the gate structure.
Abstract translation: 提供一种用于制造SONOS（氧化硅氮化物半导体）型非易失性存储器件的方法，以通过使用具有电荷陷阱层图案的氮化硅层来防止等离子体蚀刻损伤并改善电荷陷阱特性。 在衬底（100）上形成沟槽。 沟槽被充分地埋入，并且在衬底上形成隔离层（108）。 在由隔离层露出的基板上形成包括绝缘材料的第一薄膜。 在第一薄膜上形成包括氮化硅的第二薄膜图案。 在包括第二薄膜图案和隔离层的所得结构上形成作为电介质层的第三薄膜。 在第三薄膜上形成包括导电材料的第四薄膜。 包括第一薄膜的隧道绝缘层图案，第二薄膜图案的电荷陷阱层图案，第三薄膜的阻挡绝缘层图案和第四薄膜的栅电极的栅极结构（150） 通过对四个薄膜，第三薄膜，第二薄膜图案和第一薄膜进行图案化而形成。 源极/漏极（130）形成在与栅极结构相邻的衬底的表面下方。
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公开(公告)号：KR1020050095261A
公开(公告)日：2005-09-29
申请号：KR1020040020521
申请日：2004-03-25
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/02052
Abstract: 희석 에이.피.엠 수용액(An Aqueous Solution Diluted Ammonia And Peroxide Mixture)을 이용한 반도체 장치의 제조방법들을 제공한다. 이 제조방법들은 실리콘-게르마늄의 합금막을 갖는 단결정 실리콘 기저판에 희석 에이.피.엠 수용액을 사용해서 개별 소자들의 특성을 향상시킬 수 있는 방안을 제시한다. 이를 위해서, 기저판의 주 표면 상에 적어도 일 회의 성장 공정을 통해서 합금막을 형성하고, 상기 성장 공정 후 합금막의 상면에 세정 공정을 실시한다. 이때에, 상기 세정 공정은 희석 APM(Ammonia and Peroxide Mixture) 수용액을 사용해서 실시하는데, 상기 희석 APM 수용액은 수산화 암모늄(NH
4 OH), 과수(H
2 O
2 ) 및 탈 이온수(DI-Water)의 체적 비율을 1: 0.5 ~ 20 : 300 ~ 2000 중의 선택된 비율을 사용해서 형성한다. 이를 통해서, 상기 희석 에이.피.엠 수용액을 이용한 반도체 장치는 실리콘-게르마늄의 합금막에 과도한 식각을 하지 않아서 단결정 실리콘 기저판 상부의 개별 소자들의 특성을 향상시킨다.-
公开(公告)号：KR101716113B1
公开(公告)日：2017-03-15
申请号：KR1020100108669
申请日：2010-11-03
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66636 , H01L21/28518 , H01L21/76802 , H01L29/4175 , H01L29/41775 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7845 , H01L29/7848
Abstract: 본발명은샐리사이드공정이용이하고미스-얼라인(mis-align)으로인한게이트의손상을방지할수 있는반도체소자및 이의제조방법을제공한다. 본발명의반도체소자의제조방법은, 기판상에형성된게이트패턴의양측에소스및 드레인을형성하고, 상기기판상에상기소스및 드레인의노출된부분을포함하는제1 절연막패턴을형성하고, 상기소스및 드레인영역과반응시키기위해상기소스및 드레인영역의상기노출된부분상에적어도하나의금속층을증착시킴으로써상기소스및 드레인영역의상기노출된부분상에실리사이드층을형성하고, 상기소스및 드레인영역의상기노출된부분상에상기실리사이드층을형성한후에, 상기제1 절연막패턴및 상기실리사이드층을덮도록상기기판의표면상에제2 절연막을형성하고, 상기실리사이드층을노출시키기위해상기제2 절연막을식각하여상기제2 절연막내에컨택홀을형성하고, 상기컨택홀의내부를도전성물질로매립하여금속배선컨택을형성하는것을포함하되, 상기게이트패턴에대한상기소스및 드레인영역의종횡비는 3:1 이하이고, 상기소스및 드레인영역과상기게이트패턴의단차는상기기판으로부터 250Å이하이고, 상기종횡비는상기소스및 드레인영역의폭에대한상기게이트패턴의상부와상기소스및 드레인영역의상부사이의단차의비율이다.
Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。
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公开(公告)号：KR1020150144192A
公开(公告)日：2015-12-24
申请号：KR1020140073018
申请日：2014-06-16
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66545 , H01L21/3105 , H01L21/31111 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L27/0886 , H01L29/0642 , H01L29/66636 , H01L29/7812 , H01L29/7813
Abstract: 반도체장치의제조방법에서, 기판상에더미게이트절연막패턴, 더미게이트전극및 게이트마스크를포함하는더미게이트구조물을형성한다. 토즈를사용하여더미게이트구조물을커버하는층간절연막을기판상에형성한다. 게이트마스크가노출될때까지층간절연막상부를평탄화하여층간절연막패턴을형성한다. 노출된게이트마스크및 그하부의더미게이트전극및 더미게이트절연막패턴을제거하여기판상면을노출시키는개구를형성하되, 층간절연막패턴은남기면서더미게이트절연막패턴은불산(HF)을포함하는식각액을사용하여제거된다. 개구를채우는게이트구조물을형성한다.
Abstract translation: 一种制造半导体器件的方法包括以下步骤：在衬底上形成包括伪栅极绝缘图案，虚拟栅电极和栅极掩模的虚拟栅极结构; 通过在基板上使用调色硅氮烷（TOSZ）形成覆盖虚拟栅极结构的层间电介质; 通过平坦化层间电介质层的上部直到栅极掩模露出来形成层间电介质图案; 并且通过去除暴露的栅极掩模，以及在其下侧上形成伪栅电极和伪栅极绝缘图案，形成露出衬底的上表面的开口。 在离开层间介质图案的同时，通过使用包括HF的蚀刻剂来去除伪栅极绝缘图案。 形成了填充开口的门结构。
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公开(公告)号：KR1020140023763A
公开(公告)日：2014-02-27
申请号：KR1020120090179
申请日：2012-08-17
Applicant: 삼성전자주식회사
IPC: H01L21/28 , H01L21/768
CPC classification number: H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76846 , H01L21/76852 , H01L21/76865 , H01L21/76883 , H01L23/485 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Provided is a semiconductor device having a metal plug and a gap-filling insulating layer. The semiconductor device comprises: a first interlayer insulating layer on a substrate; a first barrier metal layer which penetrates the first interlayer insulating layer, and is formed on a side wall and bottom of a first contact hole exposing the substrate; and a first metal plug which is formed on the first barrier metal layer, and with which the first contact hole is filled. The top of the first barrier metal includes: the first interlayer insulating layer; a gap-filling insulating layer with which a recess region is filled, wherein the recess region is defined by a first contact which is lower than the top of the first metal plug, a side of the first metal plug, a side of the first interlayer insulating layer, and the top of the first barrier metal layer; a second interlayer insulating layer on the gap-filling insulating layer; a gap-filling insulating layer which penetrates the second interlayer insulating layer, and with which the recess region is filled; and a second contact with which a second contact hole exposing the first metal plug is filled.
Abstract translation: 提供了具有金属插塞和间隙填充绝缘层的半导体器件。 半导体器件包括：在衬底上的第一层间绝缘层; 第一阻挡金属层，其穿过第一层间绝缘层，并形成在露出基板的第一接触孔的侧壁和底部; 以及形成在所述第一阻挡金属层上并且与所述第一接触孔填充的第一金属插塞。 第一阻挡金属的顶部包括：第一层间绝缘层; 填充有凹陷区域的间隙填充绝缘层，其中所述凹部区域由比所述第一金属插塞的顶部低的第一接触部，所述第一金属插塞的一侧，所述第一中间层的一侧 绝缘层和第一阻挡金属层的顶部; 间隙填充绝缘层上的第二层间绝缘层; 间隙填充绝缘层，其穿透所述第二层间绝缘层，并且所述凹部区域被填充; 以及第二接触件，暴露第一金属插塞的第二接触孔与该第二接触件填充。
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