公开(公告)号：GB2495574A

公开(公告)日：2013-04-17

申请号：GB201212471

申请日：2012-07-13

Applicant: IBM

Inventor： GUO DECHAO ,  WONG KEITH KWONG HON ,  HAN SHU-JEN ,  YUAN JUN

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/8238

Abstract: A method of transistor fabrication includes providing a substrate 10 that has a semiconductor layer 14 having an insulator layer 18 disposed thereon. The insulator layer has openings therein to expose a surface of the semiconductor layer, each opening corresponding to a location of what will become a transistor channel region in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer 20 to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer, depositing a gate metal layer 22 overlying the gate insulator layer and implanting carbon into the channel region through the gate metal layer and the gate insulator layer to form, in an upper portion of the semiconductor layer, a carbon implanted region 15 having a concentration of carbon selected to establish a voltage threshold of the transistor. Alternatively, carbon implantation may be made through a screen oxide layer (30, figure 2).

公开(公告)号：AU2021276898A1

公开(公告)日：2022-11-10

申请号：AU2021276898

申请日：2021-04-30

Applicant: IBM

Inventor： XIE RUILONG ,  RADENS CARL ,  CHENG KANGGUO ,  LI JUNTAO ,  GUO DECHAO ,  LI TAO ,  KANG TSUNG-SHENG

IPC: H01L29/78 ,  H01L21/336

Abstract: Methods and resulting structures for nanosheet devices having asymmetric gate stacks are disclosed. A nanosheet stack (102) is formed over a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial liner (202) is formed over the nanosheet stack (102) and a dielectric gate structure (204) is formed over the nanosheet stack (102) and the sacrificial liner (202). A first inner spacer (302) is formed on a sidewall of the sacrificial layers (110). A gate (112) is formed over channel regions of the nanosheet stack (102). The gate (112) includes a conductive bridge that extends over the substrate (104) in a direction orthogonal to the nanosheet stack (102). A second inner spacer (902) is formed on a sidewall of the gate (112). The first inner spacer (302) is formed prior to the gate (112) stack, while the second inner spacer (902) is formed after, and consequently, the gate (112) stack is asymmetrical.

公开(公告)号：GB2495574B

公开(公告)日：2015-11-25

申请号：GB201212471

申请日：2012-07-13

Applicant: IBM

Inventor： GUO DECHAO ,  WONG KEITH KWONG HON ,  HAN SHU-JEN ,  YUAN JUN

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/8238

Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.

公开(公告)号：DE112012001089T5

公开(公告)日：2014-06-26

申请号：DE112012001089

申请日：2012-02-24

Applicant: IBM

Inventor： YEH CHUN-CHEN ,  GUO DECHAO ,  CAI MING ,  KULKARNI PRANITA

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

Abstract: Ein Verfahren zum Ausbilden einer Halbleiterstruktur beinhaltet ein Ausbilden einer verspannungsinduzierenden Schicht über einer oder mehreren teilfertigen Feldeffekttransistor(FET)-Einheiten, die über einem Substrat angeordnet sind, wobei die eine oder die mehreren teilfertigen FET-Einheiten Opfer-Dummy-Gate-Strukturen beinhalten; ein Planarisieren der verspannungsinduzierenden Schicht und Entfernen der Opfer-Dummy-Gate-Strukturen; und im Anschluss an das Planarisieren der verspannungsinduzierenden Schicht und an das Entfernen der Opfer-Dummy-Gate-Strukturen ein Durchführen einer Ultraviolett(UV)-Härtung der verspannungsinduzierenden Schicht, um einen Wert einer durch die verspannungsinduzierende Schicht auf Kanalbereiche der einen oder der mehreren teilfertigen FET-Strukturen aufgebrachten Ausgangsverspannung zu erhöhen.

公开(公告)号：GB2492514C

公开(公告)日：2014-06-18

申请号：GB201219007

申请日：2011-03-15

Applicant: IBM

Inventor： GUO DECHAO ,  HAENSCH WILFRIED E A ,  WANG XINHUI ,  WONG KEITH KWONG HON

IPC: H01L29/78

公开(公告)号：GB2508745A

公开(公告)日：2014-06-11

申请号：GB201402956

申请日：2012-03-06

Applicant: IBM

Inventor： GUO DECHAO ,  HAN SHU-JEN ,  WONG KEITH KWONG HON ,  YUAN JUN

IPC: H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

公开(公告)号：GB2492514B

公开(公告)日：2014-06-11

申请号：GB201219007

申请日：2011-03-15

Applicant: IBM

Inventor： GUO DECHAO ,  HAENSCH WILFRIED E A ,  WANG XINHUI ,  WONG KEITH KWONG HON

IPC: H01L29/78

公开(公告)号：DE112012003020T5

公开(公告)日：2014-05-08

申请号：DE112012003020

申请日：2012-03-06

Applicant: IBM

Inventor： GUO DECHAO ,  HAN SHU-JEN ,  WONG KEITH KWONG HON ,  YUAN JUN

IPC: H01L27/00

Abstract: In einem Ersatz-Gate-Schema wird eine durchgehende Materialschicht auf einer Bodenfläche und einer Seitenwandfläche in einem Gate-Hohlraum abgeschieden. Ein vertikaler Abschnitt der durchgehenden Materialschicht wird entfernt, um eine Gate-Komponente auszubilden, deren vertikaler Abschnitt sich nicht bis zu einer Oberseite des Gate-Hohlraums erstreckt. Die Gate-Komponente kann als Gate-Dielektrikum oder als Austrittsarbeits-Materialabschnitt eingesetzt werden, um eine Gate-Struktur auszubilden, die die Leistungsfähigkeit eines Ersatz-Gate-Feldeffekttransistors verbessert.

公开(公告)号：GB2504434A

公开(公告)日：2014-01-29

申请号：GB201320100

申请日：2012-05-18

Applicant: IBM

Inventor： GUO DECHAO ,  HAN SHU-JEN ,  WONG KEITH KWONG HON ,  YUAN JUN

IPC: H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L51/05

Abstract: A device and method for device fabrication includes forming (202) a buried gate electrode in a dielectric substrate and patterning (212) a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened (216) to define recesses in regions adjacent to the stack. The recesses are etched (218) to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi- conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited (224) in the cavities to form self-aligned source and drain regions.

公开(公告)号：GB2496964B

公开(公告)日：2013-11-20

申请号：GB201220281

申请日：2012-11-12

Applicant: IBM

Inventor： HAN SHU-JEN ,  GUO DECHAO ,  WONG KEITH KWONG HON ,  LU YU ,  CAO QING

IPC: H01L51/00 ,  H01L51/05