公开(公告)号：DE10107150A1

公开(公告)日：2002-09-26

申请号：DE10107150

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  SCHUPKE KRISTIN ,  MOLL ANETT ,  JAKUBOWSKI FRANK

IPC: C30B33/10 ,  H01L21/66 ,  C30B33/00

Abstract: Process for identifying offsets comprises inserting a substrate (102) coated with an epitaxial layer (101) in a testing device, etching the epitaxial layer faster than the offsets in an etching solution, uncovering oxide islands (103) during etching, forming offset markers (104) assigned to the uncovered oxide islands, localizing the offsets using a defect density device in the testing device, outputting a defect density distribution as a result of the testing process, and removing the tested substrate having a partially etched epitaxial layer from the testing device. An Independent claim is also included for a testing device for carrying out the above process comprising a substrate insertion device, an etching device, a localization device, an output device, and a removal device. Preferred Features: The etching process is carried out with an ammonia solution or with alkaline solutions such as TMAH, KOH, NaOH, choline, or ethylenediamine.

公开(公告)号：DE10111803A1

公开(公告)日：2002-06-27

申请号：DE10111803

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  LUETZEN JOERN

IPC: C25D7/12 ,  H01L21/288 ,  H01L21/3063 ,  H01L21/60

Abstract: Arrangement for contacting a semiconductor substrate comprises a substrate (1) having a first main surface (2) lying opposite a second main surface (3); a conducting layer (5) arranged on the first main surface; a first conducting layer (6) arranged on the conducting layer; and a first contact needle (10) inserted through the first insulating layer up to the conducting layer. An Independent claim is also included for a process for contacting a semiconductor substrate. Preferred Features: A second contact needle (11) is inserted through the first insulating layer up to the conducting layer. The first contact needle has a first electrical connection (12) and forms an electrical connection between the conducting layer and the electrical connection. A barrier layer (4) is arranged between the substrate and the conducting layer.

公开(公告)号：DE10027931C1

公开(公告)日：2002-01-10

申请号：DE10027931

申请日：2000-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  FRANOSCH MARTIN ,  LEHMANN VOLKER ,  LUETZEN JOERN

IPC: H01L21/683 ,  H01L21/3063 ,  H01L21/28 ,  H01L21/68

公开(公告)号：DE102008002653B4

公开(公告)日：2015-07-23

申请号：DE102008002653

申请日：2008-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  CHEN QIANG

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06

Abstract: Halbleiterbauelement, umfassend: eine über einem Halbleiterkörper (128, 130) angeordnete Schicht aus Isoliermaterial (134) und eine in der Schicht aus Isoliermaterial (134) angeordnete Gateelektrode (103), wobei die Gateelektrode (103) ein erstes Gebiet aus Gateelektrodenmaterial mit einer Länge, Breite, einem ersten Ende an einem Ende der Länge und einem zweiten Ende an einem Ende der Länge gegenüber dem ersten Ende umfasst; ein innerhalb des Halbleiterkörpers (128, 130) angeordnetes Sourcegebiet (106), wobei sich das Sourcegebiet (106) bei dem ersten Gebiet aus Gateelektrodenmaterial entlang der Breite des ersten Gategebiets aus Gateelektrodenmaterial befindet; ein innerhalb des Halbleiterkörpers (128, 130) angeordnetes Draingebiet (108), wobei sich das Draingebiet (108) bei dem ersten Gebiet aus Gateelektrodenmaterial entlang der Breite des ersten Gebiets aus Gateelektrodenmaterial gegenüber dem Sourcegebiet (106) befindet; eine Gateverbindung (102), die ein zweites Gebiet aus Gateelektrodenmaterial umfasst, das sich von der Breite des ersten Gategebiets weg erstreckt und elektrisch an ein Kontaktgebiet (115) gekoppelt ist, wobei das zweite Gebiet aus Gateelektrodenmaterial an das erste Gebiet aus Gateelektrodenmaterial entlang der Breite des ersten Gebiets aus Gateelektrodenmaterial zwischen dem ersten und dem zweiten Ende gekoppelt ist; und ein unter der Gateverbindung (102) angeordnetes erstes Isoliergebiet (104a).

公开(公告)号：DE102010028137A1

公开(公告)日：2010-11-11

申请号：DE102010028137

申请日：2010-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDEL UWE ,  OBERNHUBER THORSTEN ,  BIRNER ALBERT ,  EHRENTRAUT GEORG

IPC: H01L21/283 ,  H01L21/768

公开(公告)号：DE102009012594A1

公开(公告)日：2009-12-24

申请号：DE102009012594

申请日：2009-03-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  HOECKELE UWE ,  KUNSTMANN THOMAS ,  SEIDEL UWE

IPC: H01L21/60 ,  H01L23/50

公开(公告)号：DE10104742B4

公开(公告)日：2006-01-12

申请号：DE10104742

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SCHUMANN DIRK ,  LUETZEN JOERN

IPC: H01L21/762 ,  H01L21/8242

公开(公告)号：DE10326805A1

公开(公告)日：2005-01-13

申请号：DE10326805

申请日：2003-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8247

Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

公开(公告)号：DE10216614B4

公开(公告)日：2004-06-17

申请号：DE10216614

申请日：2002-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  BIRNER ALBERT ,  SEIDL HARALD ,  SCHROEDER UWE ,  JAKSCHIK STEFAN ,  GUTSCHE MARTIN

IPC: C25D11/02 ,  C25D11/32 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/318 ,  H01L21/3105 ,  H01L27/108

Abstract: Production of a thin dielectric layer (2) on a conducting substrate (1) comprises applying a thin dielectric layer on the substrate, placing in an electrochemical cell (5) filled with an electrolyte (9) and having two electrodes (6, 7), connecting the substrate with the first electrode and the second electrode with the electrolyte, and applying an electrical potential between the electrodes. The current flow between the electrolyte and substrate is controlled in an electrochemical process and is adjusted by the dielectric layer, preferably in the region of defect sites. An Independent claim is also included for an arrangement of a substrate and a dielectric layer.

公开(公告)号：DE10203674A1

公开(公告)日：2003-08-14

申请号：DE10203674

申请日：2002-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  SEIDL HARALD ,  LUETZEN JOERN ,  BIRNER ALBERT ,  SAENGER ANNETTE ,  BEITEL GERHARD

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8242 ,  H01L29/51 ,  H01L27/108 ,  H01L29/18

Abstract: Disclosed is a semiconductor component that is substantially made from a silicon material and has an insulating layer, for example, in the form of a gate insulating layer for an MOS transistor or in the form of an insulating layer of a storage cell for a dynamic component. The insulating layer preferably consists of a dielectric material whose band gap is greater than the band gap of SiO2. Materials having a metal-fluorine compound such as lithium fluoride are used in the production of the component. Particularly thin insulating layers can be produced with the disclosed material..