公开(公告)号：DE10240429A1

公开(公告)日：2004-03-18

申请号：DE10240429

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  ENDERS GERHARD ,  HEINECK LARS ,  VOIGT PETER ,  HIERLEMANN MATTHIAS ,  FISCHER BJOERN ,  FAUL JUERGEN

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

Abstract: Production of a semiconductor structure comprises applying gate stacks (GS1-GS8) onto a gate dielectric (5) over a semiconductor substrate (1), implanting a dopant (100) which is self-adjusting to the edges of the gate stack, and forming a side wall oxide (40) on exposed side walls of the gate stack with simultaneous formation of diffused doping regions (100', 110', 120', 130') under the gate edge. An Independent claim is also included for a semiconductor structure produced by the above process.

公开(公告)号：DE10226965A1

公开(公告)日：2004-01-08

申请号：DE10226965

申请日：2002-06-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANGER DIRK ,  POPP MARTIN ,  SCHLOESSER TILL ,  SESTERHENN MICHAEL

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

Abstract: In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

公开(公告)号：DE10202140A1

公开(公告)日：2003-08-07

申请号：DE10202140

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR ,  SCHUPKE KRISTIN ,  SCHILLING UWE

IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  B81C1/00

Abstract: A semiconductor component having a cavity is produced by: (i) forming a cavity in a monocrystalline silicon substrate (1), and covering walls of the cavity with a cover layer at least in an upper end region of the cavity; (ii) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (iiii) growing the covering layer only on the silicon surface. Production of a semiconductor component having a cavity comprises: (a) providing a monocrystalline silicon substrate having a silicon surface; (b) forming a cavity in the silicon substrate and covering walls of the cavity, with a cover layer at least in an upper end region of the cavity; (c) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (d) growing the covering layer only on the silicon surface to cover the cavity with the covering layer, and to form a covered cavity in the monocrystalline silicon substrate.

公开(公告)号：DE10202139A1

公开(公告)日：2003-08-07

申请号：DE10202139

申请日：2002-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  TEMMLER DIETMAR

IPC: H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: A memory cell in a substrate (105) comprises a select transistor (160) and connected trench capacitor (110) surrounded by an second isolation layer (150). A first adjacent isolation layer (235) is thinner than the second layer but prevents lateral current flow, although the formation of a parasitic FET through cell operation is possible. An Independent claim is also included for a memory chip as above.

公开(公告)号：DE10154820A1

公开(公告)日：2003-05-28

申请号：DE10154820

申请日：2001-11-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN

IPC: G03F1/00 ,  G03F9/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461

Abstract: A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

公开(公告)号：DE10131276B4

公开(公告)日：2007-08-02

申请号：DE10131276

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786

Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow I ON can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I OFF . The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

公开(公告)号：DE10310128B4

公开(公告)日：2006-08-31

申请号：DE10310128

申请日：2003-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN

IPC: H01L21/225 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

公开(公告)号：DE10339702B4

公开(公告)日：2006-07-13

申请号：DE10339702

申请日：2003-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER RALF ,  POPP MARTIN ,  FAUL JUERGEN

IPC: H01L21/336 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238

公开(公告)号：DE10154820B4

公开(公告)日：2005-06-02

申请号：DE10154820

申请日：2001-11-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN

IPC: G03F1/00 ,  G03F9/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461

Abstract: A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

公开(公告)号：DE10339702A1

公开(公告)日：2005-04-07

申请号：DE10339702

申请日：2003-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER RALF ,  POPP MARTIN ,  FAUL JUERGEN

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/8232

Abstract: Method starts with semiconductor silicon substrate (1) with two FET regions (A,B) followed by formation of stray layer over both regions. Then first implantation of first foreign ions is carried out through stray layer into both regions.Then resulting structure is simultaneously tempered to form first FET through with first profile of foreign ions. Next stray layer is removed and gate dielectric film (10a) is thermaly formed from first through profile. Then follows second implant of second foreign ions for specified formation of second through profile (TTP).