公开(公告)号：CA2118147A1

公开(公告)日：1995-04-30

申请号：CA2118147

申请日：1994-10-14

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE A ,  D HEURLE FRANCOIS M ,  HARPER JAMES M E ,  MANN RANDY W ,  MILES GLEN L ,  RAKOWSKI DONALD W D

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B31/02

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：WO2007127503A8

公开(公告)日：2008-09-04

申请号：PCT/US2007060564

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  WONG KWONG-HON ,  YANG CHIH-CHAO

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract translation: 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在衬底上的第二栅电极; 以及包括与第二栅电极重叠的一对凸缘端的着陆焊盘，其中第二栅电极的结构与着陆焊盘的结构不连续。

公开(公告)号：WO2007127503A2

公开(公告)日：2007-11-08

申请号：PCT/US2007060564

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  YANG CHIH-CHAO

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract translation: 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

公开(公告)号：WO2006113158A3

公开(公告)日：2007-03-01

申请号：PCT/US2006012904

申请日：2006-04-07

Applicant: IBM ,  YANG CHIH-CHANO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

Inventor： YANG CHIH-CHANO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIM capacitor includes a dielectric layer (140) having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer (140); a first plate of a MIM capacitor comprising a conformal conductive liner (175) formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer (190) formed over a top surface of the conformal conductive liner; and a second plate (195) of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

Abstract translation: 一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIM电容器包括具有顶表面和底表面的电介质层（140） 所述电介质层中的沟槽，所述沟槽从所述介电层（140）的顶表面延伸到所述底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫（175），沟槽的底部与电介质层的底表面共面; 绝缘层（190），形成在所述共形导电衬垫的顶表面上; 和MIM电容器的第二板（195），其包括与所述绝缘层直接物理接触的芯导体，所述沟槽中的所述芯导体填充空间未被所述共形导电衬垫和所述绝缘层填充。 该方法包括与镶嵌互连线同时形成MIM电容器的一部分。

公开(公告)号：SG165342A1

公开(公告)日：2010-10-28

申请号：SG2010064129

申请日：2008-02-20

Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM

Inventor： WUPING LIU ,  WIDODO JOHNNY ,  PETRARCA KEVIN S ,  CLEVENGER LAWRENCE A ,  WAI-KIN LI

Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer. FIG 1

公开(公告)号：SG159483A1

公开(公告)日：2010-03-30

申请号：SG2009056896

申请日：2009-08-26

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： HUI LI JING ,  PING LIU WU ,  CLEVENGER LAWRENCE A

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

公开(公告)号：DE112023002726T5

公开(公告)日：2025-04-17

申请号：DE112023002726

申请日：2023-08-07

Applicant: IBM

Inventor： XIE RUILONG ,  LANZILLO NICHOLAS ANTHONY ,  MOTOYAMA KOICHI ,  ANDERSON BRENT A ,  RIZZOLO MICHAEL ,  CLEVENGER LAWRENCE A

IPC: H10B61/00 ,  H01L23/522

Abstract: Es wird eine Rückseiten-Kontaktstruktur bereitgestellt, welche eine erste Elektrode (52) eines MRAM, die auf einer Rückseite eines Wafers vorhanden ist, direkt mit einer Source/Drain-Struktur (36) eines Transistors verbindet. Der Rückseitenkontakt ist zu der Source/Drain-Struktur (36) des Transistors sowie zu der ersten Elektrode (52) des MRAM selbstausgerichtet. Die enge Nähe zwischen dem MRAM und der Source/Drain-Struktur (36) erhöht die Geschwindigkeit der Einheit. Die MRAM-Ausbeute wird nicht beeinträchtigt, da kein Zurück-Sputtern von Rückseiten-Kontaktmetall auf den MRAM erfolgt.

公开(公告)号：SG146528A1

公开(公告)日：2008-10-30

申请号：SG2008014136

申请日：2008-02-20

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： WUPING LIU ,  WIDODO JOHNNY ,  PETRARCA KEVIN S ,  CLEVENGER LAWRENCE A ,  WAI-KIN LI

Abstract: INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer.

公开(公告)号：DE602007013472D1

公开(公告)日：2011-05-05

申请号：DE602007013472

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L ,  RADENS CARL ,  WONG KEITH K ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

公开(公告)号：SG159452A1

公开(公告)日：2010-03-30

申请号：SG2009051111

申请日：2009-07-30

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： BONILLA GRISELDA ,  TIEN CHENG ,  CLEVENGER LAWRENCE A ,  GRUNOW STEPHAN ,  CHAO-KUN HU ,  QUON ROGER A ,  ZHIGUO SUN ,  WEI-TSUI TSENG ,  YIHENG XU ,  YUN WANG ,  SANG OH HYEOK

Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiWCXNYHZ disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiWCXNYHZ disposed upon the second capping layer, wherein a + b + c + d = 1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w + x + y + z = 1.0 and w, x, y, and z are each greater than 0 and less than 1.