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公开(公告)号：KR101903509B1
公开(公告)日：2018-10-05
申请号：KR1020120075571
申请日：2012-07-11
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/778
CPC classification number: H01L21/28008 , H01L21/28587 , H01L29/42316 , H01L29/66863
Abstract: 본발명은소자의누설전류를감소시키고소자의항복전압이개선된고성능의전계효과형화합물반도체소자의제조방법에관한것으로, 상기전계효과형화합물반도체소자의제조방법은기판상에, 활성층과, 오믹층을적층하고, 상기오믹층상에제1 산화막층을형성하는단계와, 상기제1 산화막층, 상기오믹층및 상기활성층의소정영역에수직으로메사영역을형성하는단계; 상기메사영역에질화막을증착하여질화막층을형성한후, 상기메사영역을평탄화하는단계; 상기제1 산화막층상에오믹전극을형성하는단계와, 상기오믹전극이형성된반도체기판상에제2 산화막층을형성한후, 미세게이트레지스트패턴을형성하고, 제1산화막층, 질화막층및 제2 산화막층의 3층절연층을건식식각하여언더컷(under-cut) 형상의프로파일을갖는미세게이트패턴을형성하는단계와, 상기미세게이트패턴이형성된반도체기판상에공중합체레지스트를도포하여감마형게이트전극의헤드패턴을형성하여게이트리세스영역을형성하는단계및 상기게이트리세스영역이형성된반도체기판상에내열성금속을증착하여감마형게이트전극을형성하는단계를포함한다.
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公开(公告)号：KR101729653B1
公开(公告)日：2017-04-25
申请号：KR1020130166513
申请日：2013-12-30
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L29/417 , H01L29/49 , H01L29/66 , H01L29/737 , H01L29/20 , H01L29/205
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786
Abstract: 본발명은질화물반도체소자에관한것으로관통비아홀들을갖는기판, 상기기판상에차례로적층되는제 1 및제 2 질화물반도체층들, 상기제 2 질화물반도체층상에제공되는드레인전극들및 소스전극들및 상기제 2 질화물반도체층상에제공되고, 상기드레인전극들상에제공되는상부비아홀들을갖는절연패턴을포함하고, 상기관통비아홀들은상기제 1 및제 2 질화물반도체층들내로연장되어상기소스전극들의하면을노출하는질화물반도체소자가제공된다.
Abstract translation: 本发明涉及一种氮化物半导体器件，其包括具有通孔的衬底，顺序地堆叠在衬底上的第一和第二氮化物半导体层，设置在第二氮化物半导体层上的漏极和源极， 2氮化物半导体层并且具有设置在漏电极上的上通路孔，通路孔延伸到第一和第二氮化物半导体层中以暴露源电极的下表面 提供氮化物半导体器件。
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公开(公告)号：KR101616156B1
公开(公告)日：2016-04-27
申请号：KR1020120018591
申请日：2012-02-23
Applicant: 한국전자통신연구원
IPC: H01L29/812 , H01L21/338
Abstract: 본발명은질화물전자소자및 그제조방법에관한것으로서, 상세하게는갈륨(Gallium: Ga), 알루미늄(Aluminum: Al), 인듐(Indium: In) 등의 3족원소및 질소를포함하는 3족질화물(III-Nitride) 반도체전자소자에서사용되는반절연성질화갈륨(GaN)층의재성장기술(Epitaxially Lateral Over-Growth: ELOG)을통해다양한형태의질화물집적구조를동일기판위에구현할수 있는질화물전자소자및그 제조방법에관한것이다.
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公开(公告)号：KR1020150077735A
公开(公告)日：2015-07-08
申请号：KR1020130166513
申请日：2013-12-30
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L29/417 , H01L29/49 , H01L29/66 , H01L29/737 , H01L29/20 , H01L29/205
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786 , H01L29/205 , H01L29/41725 , H01L29/49
Abstract: 본발명은질화물반도체소자에관한것으로관통비아홀들을갖는기판, 상기기판상에차례로적층되는제 1 및제 2 질화물반도체층들, 상기제 2 질화물반도체층상에제공되는드레인전극들및 소스전극들및 상기제 2 질화물반도체층상에제공되고, 상기드레인전극들상에제공되는상부비아홀들을갖는절연패턴을포함하고, 상기관통비아홀들은상기제 1 및제 2 질화물반도체층들내로연장되어상기소스전극들의하면을노출하는질화물반도체소자가제공된다.
Abstract translation: 本发明涉及一种氮化物半导体器件。 它包括具有穿透通孔的基片，连续堆叠在基片上的第一和第二氮化物半导体层，设置在第二氮化物半导体层上的漏电极和源电极以及设置在第二氮化物半导体上的绝缘图案 并且具有设置在漏电极上的上通孔。 穿透通孔延伸到第一和第二氮化物半导体层的内部并暴露源电极的下表面。
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公开(公告)号：KR1020150068729A
公开(公告)日：2015-06-22
申请号：KR1020130154740
申请日：2013-12-12
Applicant: 한국전자통신연구원
IPC: H01L23/467 , H01L23/473 , H01L23/367 , H01L23/427 , H05K7/20
CPC classification number: H01L23/467 , H01L23/3677 , H01L23/427 , H01L23/473 , H05K7/20336
Abstract: 본발명은평판방열소자의구조를제공한다. 이평판방열소자는작동유체로채워진진공의관통영역을갖는평판, 및상기평판상에배치된복수개의히트싱크핀들을포함하고, 상기관통영역은모세관력에의해상기작동유체의유통경로를제공하는복수개의그루브들을포함할수 있다.
Abstract translation: 提供一种平板式散热装置。 平板式散热装置包括：平板，其具有填充有工作流体的真空穿透区域，以及布置在平板上的散热销。 穿透区域包括由毛细管力产生的工作流体的流动路径。
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Patent Agency Ranking
公开(公告)号：KR1020140075946A
公开(公告)日：2014-06-20
申请号：KR1020120143702
申请日：2012-12-11
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/778 , H01L29/402 , H01L29/42316 , H01L29/66431
Abstract: A high electron mobility transistor is provided. The transistor includes a source electrode and a drain electrode disposed on a substrate to be spaced apart; a T-shaped gate electrode disposed between the source electrode and the drain electrode on the substrate; and a plurality of insulating films interposed between the substrate and the T-shaped gate electrode. The plurality of insulating films is composed of a first insulating film, a second insulating film, and a third insulating film. The third insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the leg part of the T-shaped gate electrode. The second insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the third insulating film. The first insulating film and the third insulating film stacked in order are interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the second insulating film.
Abstract translation: 提供高电子迁移率晶体管。 晶体管包括设置在基板上的源电极和漏电极以被间隔开; 设置在基板上的源电极和漏电极之间的T字栅电极; 以及插入在所述基板和所述T形栅电极之间的多个绝缘膜。 多个绝缘膜由第一绝缘膜，第二绝缘膜和第三绝缘膜构成。 第三绝缘膜插入到基板和T形栅电极的头部之间，以与T形栅电极的腿部接触。 第二绝缘膜插入到基板和T形栅电极的头部之间以与第三绝缘膜接触。 按顺序堆叠的第一绝缘膜和第三绝缘膜介于基板和T形栅电极的头部之间以与第二绝缘膜接触。
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公开(公告)号：KR1020140048026A
公开(公告)日：2014-04-23
申请号：KR1020130029769
申请日：2013-03-20
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
CPC classification number: H01L21/76898 , H01L21/76877 , H01L23/481 , H01L23/535
Abstract: A semiconductor device according to the concept of the present invention may include a substrate having a lower via hole; an epi layer which has an opening part for exposing the upper surface of the substrate; a semiconductor chip which is provided on the upper surface of the substrate and includes a first electrode, a second electrode, and a third electrode; an upper metal layer connected to the first electrode; a support plate which is arranged on the upper metal layer and has an upper via hole; an upper pad which is arranged on the support substrate and is extended to the inner part of the upper via hole; a lower pad which is arranged in the opening pad and is connected to the second electrode; and a lower metal layer which covers the lower surface of the substrate and is connected to the lower pad through the lower via hole.
Abstract translation: 根据本发明的概念的半导体器件可以包括具有下通孔的衬底; 外延层，其具有用于使基板的上表面露出的开口部; 半导体芯片，其设置在所述基板的上表面，并且包括第一电极，第二电极和第三电极; 连接到第一电极的上金属层; 支撑板，其设置在上金属层上并具有上通孔; 上垫，其布置在所述支撑基板上并延伸到所述上通孔的内部; 下垫，其布置在所述开口垫中并连接到所述第二电极; 以及覆盖基板的下表面并通过下通孔连接到下焊盘的下金属层。
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公开(公告)号：KR1020140041357A
公开(公告)日：2014-04-04
申请号：KR1020130113746
申请日：2013-09-25
Applicant: 한국전자통신연구원
IPC: G05F1/46
CPC classification number: H02M3/1582 , H02H7/1213 , H02M1/44
Abstract: The present invention relates to a system of supplying constant-current DC power to various serial loads which are connected in series. The present invention comprises a constant-current DC power supply part which outputs a preset direct current, a load connection part which has the same rated current as a constant current source, a load connection part which has a less rated current than the constant current source, a load connection part which has a greater rated current than the constant current source, a load connection part which changes from case to case and has a less or greater rated current than a constant current source, and a circuit and an algorithm which protect or control them.
Abstract translation: 本发明涉及向串联连接的各种串联负载提供恒流直流电力的系统。 本发明包括输出预设直流电流的恒流直流电源部分，与恒流源具有相同额定电流的负载连接部分，具有比恒定电流源更小的额定电流的负载连接部分 具有比恒定电流源更大的额定电流的负载连接部，负载连接部，其从情况变化到具有比恒定电流源小的或更大的额定电流;以及电路和算法，其保护或 控制他们
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公开(公告)号：KR1020130093996A
公开(公告)日：2013-08-23
申请号：KR1020120015292
申请日：2012-02-15
Applicant: 한국전자통신연구원
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: PURPOSE: An impedance matching circuit including passive elements for controlling the matching property, an amplification circuit and a manufacturing method of a variable capacitor are provided to modify the characteristic value of passive elements included in the multi-staged impedance matching circuit, so that a broadband matching realizes. CONSTITUTION: A first variable inductor part (L1) is connected between the output terminal of a first node (N1) and an amplifying unit (AMP). A second variable inductor part (L2) is connected between the first node and a second Node (N2). The inductance value of the first variable inductor part and the second variable inductor part is determined according to the number and the length of wires. A first variable capacitor portion (C1) is connected between the first node and a ground voltage platform. A second variable capacitor portion (C2) is connected between the second node and the ground voltage platform. [Reference numerals] (AMP) Power amplifying unit
Abstract translation: 目的：提供一种阻抗匹配电路，其包括用于控制匹配特性的无源元件，放大电路和可变电容器的制造方法，以修改包括在多级阻抗匹配电路中的无源元件的特性值，使得宽带 匹配实现。 构成：第一可变电感器部分（L1）连接在第一节点（N1）的输出端和放大单元（AMP）之间。 第二可变电感器部分（L2）连接在第一节点和第二节点（N2）之间。 根据导线的数量和长度确定第一可变电感器部分和第二可变电感器部分的电感值。 第一可变电容器部分（C1）连接在第一节点和地电压平台之间。 第二可变电容器部分（C2）连接在第二节点和地电压平台之间。 （附图标记）（AMP）功率放大单元
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公开(公告)号：KR1020130066934A
公开(公告)日：2013-06-21
申请号：KR1020110133715
申请日：2011-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
CPC classification number: H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: PURPOSE: A semiconductor device including a step gate electrode and a manufacturing method thereof are provided to increase a breakdown voltage by using optical photoresist and two nitride layers. CONSTITUTION: A cap layer(211) is formed on a semiconductor substrate. An active area is formed by etching a part of the cap layer. A resist pattern is formed on the active area and the cap layer. A step gate electrode(225) is formed by depositing heat-resistant metal. An insulation layer(227) is deposited by removing a gate head pattern.
Abstract translation: 目的：提供包括步进栅电极及其制造方法的半导体器件，以通过使用光致抗蚀剂和两个氮化物层来增加击穿电压。 构成：在半导体衬底上形成覆盖层（211）。 通过蚀刻盖层的一部分形成有源区。 在有源区域和盖层上形成抗蚀剂图案。 通过沉积耐热金属形成步进栅电极（225）。 通过去除栅极头图案来沉积绝缘层（227）。
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