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公开(公告)号：KR1020110017957A
公开(公告)日：2011-02-23
申请号：KR1020090075515
申请日：2009-08-17
Applicant: 한국전자통신연구원
IPC: H01L35/00
Abstract: PURPOSE: A thermoelectric-generator is provided to improve thermal efficiency by increasing electrical conductivity while reducing thermal conductivity. CONSTITUTION: A heat absorbing member(110) absorbs heat supplied from outside. A heat radiating member(130) emits the heat from the heat sink to outside. A wire part(120) connects the heat absorbing member to the heat radiating member through a plurality of nano wires having curvature A thermoelectric device applies magnetic field to the wire part to make a movement path for electronics and phonon different. The heat absorbing member, a heat radiating member, and a wire part are formed on the same substrate.
Abstract translation: 目的：提供一种热电发生器，通过增加电导率同时降低热导率来提高热效率。 构成：吸热构件（110）吸收从外部供应的热量。 散热构件（130）将来自散热器的热量发射到外部。 电线部分（120）通过具有曲率的多个纳米线将吸热件连接到散热构件。热电装置向电线部分施加磁场，以使电子和声子的移动路径不同。 吸热部件，散热部件和导线部分形成在同一基板上。
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公开(公告)号：KR1020100064854A
公开(公告)日：2010-06-15
申请号：KR1020080123488
申请日：2008-12-05
Applicant: 한국전자통신연구원
CPC classification number: H04W84/18
Abstract: PURPOSE: A sensor node with self-charging function and a method for operating the same are provided to install power generation unit and power storage unit to the sensor node for monitoring physical change amount of neighboring environment at a real time, thereby providing power stably and continuously. CONSTITUTION: A sensor unit(210) monitors an event according to external environment. A control unit(240) determines critical situation through comparison between a sensing signal and preset critical value corresponding to the event. A power control unit(220) supplies driving power to the sensor unit and the control unit. The power control unit determines power value available for output. If the power value available for output is smaller than minimum drive power value, the power control unit performs generation and storage of electricity.
Abstract translation: 目的：提供一种具有自充电功能的传感器节点及其操作方法，将发电单元和蓄电单元安装到传感器节点，实时监控相邻环境的物理变化量，从而稳定地提供电力 不断。 构成：传感器单元（210）根据外部环境监视事件。 控制单元（240）通过比较感测信号和对应于该事件的预设临界值来确定关键情况。 电力控制单元（220）向传感器单元和控制单元提供驱动电力。 功率控制单元确定可用于输出的功率值。 如果可用于输出的功率值小于最小驱动功率值，则功率控制单元执行发电和存储电力。
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公开(公告)号：KR1020100030335A
公开(公告)日：2010-03-18
申请号：KR1020080089237
申请日：2008-09-10
Applicant: 한국전자통신연구원
CPC classification number: G01N33/54373 , B01L3/502761 , B01L2200/143 , B01L2300/0636 , B01L2300/0645 , B01L2300/0867 , B01L2300/163 , B01L2400/0415 , G01N27/4145
Abstract: PURPOSE: A device and a method for detecting biomolecules are provided to detect biomolecules with high-ionic strength by measuring a current change flowing in a channel area of a Field Effect Transistor. CONSTITUTION: A device for detecting biomolecules comprises a FET(12), a micro fluid supply unit(14), and a biomolecules detecting unit(18). The FET comprises a substrate, a source, a drain electrode, a channel area, and a probe molecule. The micro fluid supply unit selectively supplies reaction solution of high-ionic density to the channel area of the FET. The biomolecules detecting unit measures a first current value of the channel area of the FET in which the probe molecule is fixed. The biomolecules detecting unit measures a second current value of the channel area of the FET in which the probe molecule and a target molecule are fixed. And the biomolecules detecting unit detects the target molecule.
Abstract translation: 目的：提供一种用于检测生物分子的装置和方法，通过测量在场效应晶体管的通道区域中流动的电流变化来检测具有高离子强度的生物分子。 构成：用于检测生物分子的装置包括FET（12），微流体供应单元（14）和生物分子检测单元（18）。 FET包括衬底，源极，漏极，沟道区和探针分子。 微流体供应单元选择性地将高离子密度的反应溶液提供给FET的通道区域。 生物分子检测单元测量探针分子固定的FET的沟道面积的第一电流值。 生物分子检测单元测量探针分子和靶分子固定的FET的沟道面积的第二电流值。 并且生物分子检测单元检测靶分子。
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公开(公告)号：KR100940524B1
公开(公告)日：2010-02-10
申请号：KR1020070129581
申请日：2007-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: G01N27/4145 , H01L29/66818 , H01L29/7853
Abstract: 본 발명은 반도체 기술을 이용한 FET(Field-effect transistor) 센서에 관한 것으로, 좀더 구체적으로는 FET 센서의 민감도를 개선시키기 위하여 핀 구조를 이용하는 FET 센서 및 그 제조방법에 관한 것이다. 본 발명에 따른 반도체 FET 센서를 제조하는 방법은, 반도체 기판을 제공하는 단계와, 상기 반도체 기판상에 핀 구조를 갖는 센서 구조체를 형성하는 단계와, 상기 센서 구조체에 전기적 오믹 콘택을 위한 이온을 주입하고 금속 전극을 증착하는 단계와, 표적물질과 특이성 결합하는 감지물질을 상기 핀 구조의 양쪽 측벽에 고정화시키는 단계와, 상기 표적물질이 상기 핀 구조를 지나가도록 하는 통로를 상기 센서 구조체 위에 형성하는 단계를 포함한다.
반도체 FET 센서, 핀 구조, 바이오 센서, SOI 기판, 벌크 기판-
公开(公告)号：KR1020080051010A
公开(公告)日：2008-06-10
申请号：KR1020070094687
申请日：2007-09-18
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/66825 , H01L21/28273 , H01L21/67063 , H01L29/42324 , H01L29/513
Abstract: A highly-integrated semiconductor memory device and a manufacturing method thereof are provided to correctly read data by suppressing a leakage current generated as the semiconductor memory device is highly integrated. A source/drain electrode(220A) are formed on a silicon substrate to form a schottky junction with a channel region(220B). A floating gate composed of plural silicon nanodots(260A) is formed on the substrate of the channel region. The silicon nanodot is made of a silicon compound as a basal body, and a gate dielectric layer(270) is formed on the floating gate. A tunneling dielectric layer(250) is formed between the substrate of the channel region and the floating gate, and a control gate(280) is formed on the floating gate.
Abstract translation: 提供了一种高度集成的半导体存储器件及其制造方法，以通过抑制半导体存储器件高集成度时产生的漏电流来正确读取数据。 源极/漏极（220A）形成在硅衬底上以与沟道区（220B）形成肖特基结。 在沟道区的基板上形成由多个硅纳米点（260A）构成的浮置栅极。 硅纳米棒由硅化合物作为基体，在浮栅上形成栅介质层（270）。 在沟道区的衬底和浮置栅极之间形成隧穿电介质层（250），并且在浮动栅极上形成控制栅极（280）。
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Patent Agency Ranking
公开(公告)号：KR1020080051009A
公开(公告)日：2008-06-10
申请号：KR1020070094686
申请日：2007-09-18
Applicant: 한국전자통신연구원
IPC: H01L27/108 , H01L21/8242 , H01L29/47
CPC classification number: H01L27/108 , H01L27/095 , H01L29/66257
Abstract: A semiconductor memory device and a driving method thereof are provided to store an electric charge in a channel region by using a schottky barrier formed at an interface between a channel region and a source/drain electrode. A gate(160) is formed over a channel region(130) of a silicon substrate(100). A source electrode(110) and a drain electrode(120) are formed on the silicon substrate to form a schottky junction with the channel region. An electric charge is stored in a schottky barrier formed between the source electrode and the drain electrode. The source electrode and the drain electrode are made of same or different metal silicide. A level of the schottky junction between the channel region and the source electrode is identical to or different from a level of the schottky barrier between the channel region and the drain electrode.
Abstract translation: 提供一种半导体存储器件及其驱动方法，通过使用在沟道区域和源极/漏极之间的界面处形成的肖特基势垒来在沟道区域中存储电荷。 在硅衬底（100）的沟道区（130）上形成栅极（160）。 在硅衬底上形成源电极（110）和漏电极（120），以形成与沟道区域的肖特基结。 在源电极和漏电极之间形成的肖特基势垒中存储电荷。 源电极和漏电极由相同或不同的金属硅化物制成。 沟道区和源电极之间的肖特基结的电平与沟道区和漏电极之间的肖特基势垒的电平相同或不同。
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公开(公告)号：KR100777101B1
公开(公告)日：2007-11-19
申请号：KR1020060074492
申请日：2006-08-08
Applicant: 한국전자통신연구원
IPC: H01L21/335 , H01L29/872
Abstract: 본 발명은 비등방 에칭을 통해 생성되는 실리콘 (111)면(결정구조를 갖는 반도체에서 그 결정방향을 나타내는 밀러 지수)에 쇼트키 접합을 형성시켜 안정적이고, 전자에 대해 낮은 쇼트키 장벽을 갖는 고성능의 N-형 쇼트키 장벽 관통 트랜지스터를 제작하기 위한 것이다. 이를 위하여, 본 발명의 일실시 예에 따른 쇼트키 장벽 관통 트랜지스터는, 기판; 상기 기판 상에 형성된 소오스 및 드레인; 상기 소오스와 드레인 사이에 형성된 채널; 상기 채널 상에 순차적으로 형성된 게이트 절연막 및 게이트 전극;상기 게이트 절연막 및 게이트 전극의 양측 벽에 형성된 측벽 절연막을 포함하되, 상기 소오스 및 드레인과 상기 채널의 경계면은 실리콘 (111)면을 가지며, 상기 실리콘 (111)면, 소오스 및 드레인이 금속 물질로 실리사이드화되어 쇼트키 접합된다.
쇼트키 장벽 관통, 비등방 식각-
公开(公告)号：KR100776648B1
公开(公告)日：2007-11-19
申请号：KR1020060123236
申请日：2006-12-06
Applicant: 한국전자통신연구원
IPC: H01L29/775
CPC classification number: H01L33/0004 , H01L27/15 , H01L33/06 , H01L33/16 , H01L33/34
Abstract: A silicon-based optical device and a method for manufacturing the same are provided to simplify a manufacturing process by using a general CMOS(Complementary Metal-Oxide Semiconductor) manufacturing method. A first and second transistors(100,101) are formed by using different conductive materials based on a silicon substrate(110), respectively. An active layer(119) is formed within the substrate between the first and second transistors. The active layer is formed with one quantum dot which is selected from a group including a silicon quantum dot formed within a silicon nitride layer, a silicon quantum dot formed within a silicon oxide layer, and a compound quantum dot. The compound quantum dot is selected from a group including GaAs, InAs, InGaAs, InAlAs, and InP. Each of the first and second transistors includes a gate insulating layer(113) formed on the substrate, gate electrodes(114A,114B) formed on the gate insulating layer, and a junction area(116) formed within the substrate exposed toward one side of the gate electrode.
Abstract translation: 提供硅基光学器件及其制造方法，以通过使用通用CMOS（互补金属氧化物半导体）制造方法来简化制造工艺。 第一和第二晶体管（100,101）分别通过使用基于硅衬底（110）的不同导电材料形成。 在第一和第二晶体管之间的衬底内形成有源层（119）。 有源层形成有一个量子点，其从包括在氮化硅层内形成的硅量子点的点，在氧化硅层内形成的硅量子点和化合物量子点组成。 化合物量子点选自包括GaAs，InAs，InGaAs，InAlAs和InP的组。 第一晶体管和第二晶体管中的每一个包括形成在基板上的栅极绝缘层（113），形成在栅极绝缘层上的栅电极（114A，114B）和形成在基板内的接合区域（116） 栅电极。
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公开(公告)号：KR100698013B1
公开(公告)日：2007-03-23
申请号：KR1020050119409
申请日：2005-12-08
Applicant: 한국전자통신연구원
IPC: H01L29/812
CPC classification number: H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
Abstract: A schottky barrier tunneling transistor and a method for manufacturing the same are provided to minimize leakage current of a gate by recovering damage of an insulating layer of a gate sidewall of the same according to a silicide process. A channel layer is formed on an upper surface of an SOI substrate(6). A source and drain(9) is formed at both ends of the channel layer on the SOI substrate. A gate(12) is formed on the channel layer. A first gate insulating layer is formed to shield the gate from the source and drain and the channel layer. A second gate insulating layer is formed between the first gate insulating layer and the gate.
Abstract translation: 提供肖特基势垒隧道晶体管及其制造方法，以通过根据硅化物处理来恢复其栅极侧壁的绝缘层的损坏来最小化栅极的漏电流。 沟道层形成在SOI衬底（6）的上表面上。 源极和漏极（9）形成在SOI衬底上的沟道层的两端。 在沟道层上形成栅极（12）。 形成第一栅极绝缘层以屏蔽栅极与源极和漏极以及沟道层。 在第一栅极绝缘层和栅极之间形成第二栅极绝缘层。
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公开(公告)号：KR100586178B1
公开(公告)日：2006-06-07
申请号：KR1020030097061
申请日：2003-12-26
Applicant: 한국전자통신연구원
IPC: H01L27/08 , H01L27/12 , H01L31/108
CPC classification number: H01L29/47
Abstract: 본 발명은 SOI 기판을 이용한 쇼트키 장벽 관통 트랜지스터 및 그 제조방법으로, 종래의 불순물을 주입하여 소스 및 드래인 영역을 구성하는 방식의 전계효과 트랜지스터 대신에 소스 및 드레인을 실리콘과 금속의 반응 물질인 실리사이드로 대체하여 금속-반도체간에 형성되는 쇼트키 장벽을 이용하여 제작하는 쇼트키 장벽 관통 트랜지스터를 제공한다.
쇼트키, SOI, 실리사이드, MOSFET
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