公开(公告)号：GB2490606B

公开(公告)日：2015-06-24

申请号：GB201208994

申请日：2011-02-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

IPC: H01L21/02 ,  H01L31/18

Abstract: A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture.

公开(公告)号：GB2496970B

公开(公告)日：2014-06-11

申请号：GB201220562

申请日：2012-11-15

Applicant: IBM

Inventor： HEKMATSHOARTABARI BAHMAN ,  SHAHRJERDI DAVOOD ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

IPC: H01L27/15 ,  H01L27/12 ,  H01L33/00 ,  H01L33/62

Abstract: A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array.

公开(公告)号：GB2495828B

公开(公告)日：2013-09-25

申请号：GB201218439

申请日：2012-10-15

Applicant: IBM

Inventor： SHAHRJERDI DAVOOD ,  HEKMATSHOARTABARI BAHMAN ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

IPC: H01L31/0725

Abstract: A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline.

公开(公告)号：GB2494014B

公开(公告)日：2013-07-17

申请号：GB201209766

申请日：2012-06-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  LIU XIAO HU ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

公开(公告)号：GB2496970A

公开(公告)日：2013-05-29

申请号：GB201220562

申请日：2012-11-15

Applicant: IBM

Inventor： HEKMATSHOARTABARI BAHMAN ,  SHAHRJERDI DAVOOD ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM G

IPC: H01L27/15 ,  H01L27/12 ,  H01L33/00 ,  H01L33/62

Abstract: A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material 804 originally grown thereupon; and bonding the removed layer of inorganic LED material 804 to an active matrix, thin film transistor (TFT) backplane array 802. Also disclosed is the active matrix light emitting diode array produced from said method. The inorganic LED material 804 may be removed from the base substrate by a method of spalling, wherein at least one or more stress layers are formed on the inorganic LED material layer, a flexible handle layer is formed on the one or more stress layers, and applying a force to the flexible handle layer so as to separate the stress layer and at least a portion of the inorganic LED material layer from the base substrate. The inorganic LED material layer 804 may be bonded to the active matrix TFT backplane array 802 by a process of cold welding. The inorganic LED material layer 804 may be patterned once bonded to the active matrix TFT backplane array 802, where a further inorganic LED material layer 804b can be bonded to the backplane array 802 to produce an array of LED elements 804a,804b, wherein the further inorganic LED material layer 804b is produced by the same method as the first inorganic LED material layer 804a.

公开(公告)号：DE112011100105T5

公开(公告)日：2012-10-31

申请号：DE112011100105

申请日：2011-02-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH ,  LAURO PAUL A ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L21/304 ,  B28D5/00

Abstract: Ein Verfahren zum Abspalten einer Schicht von einem Block eines Halbleitersubstrats beinhaltet Ausbilden einer Metallschicht auf dem Block des Halbleitersubstrats, wobei eine Zugspannung in der Metallschicht so eingerichtet ist, dass ein Bruch in dem Block verursacht wird; und Entfernen der Schicht von dem Block an dem Bruch. Ein System zum Abspalten einer Schicht von einem Block eines Halbleitersubstrats beinhaltet eine Metallschicht, die auf dem Block des Halbleitersubstrats ausgebildet ist, wobei eine Zugspannung in der Metallschicht so eingerichtet ist, dass ein Bruch in dem Block verursacht wird, und wobei die Schicht so eingerichtet ist, dass sie an dem Bruch von dem Block entfernt wird.

公开(公告)号：CA2783626A1

公开(公告)日：2011-09-01

申请号：CA2783626

申请日：2011-02-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

IPC: H01L31/042 ,  H01L31/06

Abstract: A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single-junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

公开(公告)号：AT500610T

公开(公告)日：2011-03-15

申请号：AT03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD ,  RAINEY BETH ,  SADANA DEVENDRA

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：AU2020385351A1

公开(公告)日：2022-04-21

申请号：AU2020385351

申请日：2020-11-10

Applicant: IBM

Inventor： HOLMES STEVEN ,  SADANA DEVENDRA ,  HART SEAN ,  BEDELL STEPHEN ,  LI NING ,  GUMANN PATRYK

IPC: H01L39/02 ,  B82Y10/00 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer (410), a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region (240) surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate (204) is formed. A sensing region gate (202) is formed by coupling the semiconductor layer with a second metal layer. A chemical potential gate (208, 210) is also formed. A nanorod contact (206, 212) using the second metal within the portion of the device region outside the sensing region is formed.

公开(公告)号：DE112019000533T5

公开(公告)日：2020-10-08

申请号：DE112019000533

申请日：2019-01-15

Applicant: IBM

Inventor： DELIGIANNI HARIKLIA ,  LEE KO-TAO ,  LI NING ,  SADANA DEVENDRA

IPC: A61N5/06

Abstract: Sonden enthalten einen Sondenkörper, der zum Eindringen in biologisches Gewebe geeignet ist. Innerhalb des Sondenkörpers sind Hochleistungs-Lichtquellen angeordnet. Jede Hochleistungs-Lichtquelle hat eine ausreichend hohe optische Ausgangsleistung zum Auslösen einer lichtempfindlichen Reaktion in benachbarten Geweben und die Ausgangsleistung hingegen nicht so hoch sein darf, dass eine gesamte Wärmemenge mehrerer Lichtquellen zu einem störenden Temperaturanstieg in den benachbarten Geweben führen könnte.