公开(公告)号：DE112011100421T5

公开(公告)日：2012-11-22

申请号：DE112011100421

申请日：2011-03-15

Applicant: IBM

Inventor： GUO DECHAO ,  HAENSCH WILFRIED E ,  WANG XINHUI ,  WONG KEITH KWONG HON

IPC: H01L29/78 ,  H01L23/48

Abstract: Ein Verfahren zum Bilden eines Feldeffekttransistors umfasst das Bilden eines Gate-Stapels, eines Abstandhalters in Nachbarschaft zu gegenüber liegenden Seiten des Gate-Stapels, einer Silicid-Source-Zone und einer Silicid-Drain-Zone auf gegenüberliegenden Seiten des Abstandhalters, das epitaxiale Anwachsenlassen von Silicium auf der Source-Zone und der Drain-Zone; das Bilden einer Deckschicht auf dem Gate-Stapel und dem Abstandhalter, das Entfernen eines Teils der Deckschicht, um einen Teil der Hartmaskenschicht frei zu legen, das Entfernen der frei liegenden Teile der Hartmaskenschicht, um eine Siliciumschicht des Gate-Stapels frei zu legen, das Entfernen frei liegenden Siliciums, um einen Teil einer Metallschicht des Gate-Stapels, die Source-Zone und die Drain-Zone frei zu legen; und das Aufbringen eines leitfähigen Materials auf die Metallschicht des Gate-Stapels, die Silicid-Source-Zone und die Silicid-Drain-Zone.

公开(公告)号：DE102004016700A1

公开(公告)日：2004-11-18

申请号：DE102004016700

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEHAVEN PATRICK W ,  AGNELLO PAUL D ,  WONG KEITH KWONG HON ,  HUANG HSIANG-JEN ,  MURPHY RICHARD J ,  DZIOBKOWSKI CHET ,  CLEVENGER LAWRENCE ,  LAVOIE CHRISTIAN ,  ROVEDO NIVO ,  FANG SUNFEI

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

公开(公告)号：AU2002216238A1

公开(公告)日：2002-07-24

申请号：AU2002216238

申请日：2001-12-21

Applicant: IBM

Inventor： CABRAL CYRIL ,  HSU LOUIS LU-CHEN ,  WONG KEITH KWONG HON ,  CLEVENGER LAWRENCE

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L27/06 ,  H01L23/64

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

公开(公告)号：GB2508745B

公开(公告)日：2015-10-07

申请号：GB201402956

申请日：2012-03-06

Applicant: IBM

Inventor： GUO DECHAO ,  HAN SHU-JEN ,  WONG KEITH KWONG HON ,  YUAN JUN

IPC: H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

公开(公告)号：GB2497046A

公开(公告)日：2013-05-29

申请号：GB201304474

申请日：2011-08-18

Applicant: IBM

Inventor： WONG KEITH KWONG HON ,  GUO DECHAO

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

公开(公告)号：GB2496964A

公开(公告)日：2013-05-29

申请号：GB201220281

申请日：2012-11-12

Applicant: IBM

Inventor： HAN SHU-JEN ,  GUO DECHAO ,  WONG KEITH KWONG HON ,  LU YU ,  CAO QING

IPC: H01L51/00 ,  H01L51/05

Abstract: A fin structure has a length and a width and is located on a substrate 10, the fin structure includes a vertical alternating stack of a first isoelectric point material layer 30 having a first isoelectric point and a second isoelectric material layer 40 having a second isoelectric point less than the first isoelectric point; the first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points; carbon nanotubes 50 are given a charge by an ionic surfactant such that they are attracted to one of the first isoelectric point material layer 30 or the second isoelectric point material layer 40 and repelled by the other; the carbon nanotubes 50 will attach to the attractive of the two layers aligning lengthwise along the sidewall of the attractive layers. A method of forming said structure is also disclosed, it further discloses that the fin structure is immersed in a solution containing the carbon nanotubes 50, the solution having a pH between the first and second isoelectric points. The fin structure may then have a gate dielectric 60 and gate electrode 70 selectively deposited thereon, where source and drain electrodes may also be selectively deposited such that the fin structure becomes part of the field effect transistor with the carbon nanotubes 50 acting as the semiconducting channel.

公开(公告)号：GB2492514A

公开(公告)日：2013-01-02

申请号：GB201219007

申请日：2011-03-15

Applicant: IBM

Inventor： GUO DECHAO ,  HAENSCH WILFRIED E ,  WANG XINHUI ,  WONG KEITH KWONG HON

IPC: H01L29/78

Abstract: A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

公开(公告)号：DE10393309T5

公开(公告)日：2005-12-29

申请号：DE10393309

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CABRAL CYRIL JR ,  IGGULDEN ROY C ,  MCSTAY IRENE LENNOX ,  CLEVENGER LAWRENCE A ,  WANG YUN YU ,  WONG KEITH KWONG HON ,  ROBL WERNER ,  GLUSCHENKOV OLEG ,  MALIK RAJEEV ,  SCHUTZ RONALD J

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：AU2003272647A8

公开(公告)日：2004-04-08

申请号：AU2003272647

申请日：2003-09-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NING XIAN J ,  WONG KEITH KWONG HON

IPC: H01L21/02 ,  H01L21/316 ,  H01L21/768

Abstract: A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242) .

公开(公告)号：GB2495574B

公开(公告)日：2015-11-25

申请号：GB201212471

申请日：2012-07-13

Applicant: IBM

Inventor： GUO DECHAO ,  WONG KEITH KWONG HON ,  HAN SHU-JEN ,  YUAN JUN

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/8238

Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.