公开(公告)号：FR2954584B1

公开(公告)日：2013-07-19

申请号：FR0906233

申请日：2009-12-22

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： FENOUILLET BERANGER CLAIRE ,  DENORME STEPHANE ,  CORONEL PHILIPPE

IPC: H01L21/762 ,  H01L23/12

公开(公告)号：FR2928490B1

公开(公告)日：2011-04-15

申请号：FR0851494

申请日：2008-03-07

Applicant: ST MICROELECTRONICS SA

Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  MARTY MICHEL ,  BOPP MATTHIEU

IPC: H01L21/00 ,  H01L31/0232

公开(公告)号：FR2918795A1

公开(公告)日：2009-01-16

申请号：FR0756447

申请日：2007-07-12

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  BELREDON XAVIER

IPC: H01L27/146 ,  H01L31/02 ,  H01L31/18

Abstract: L'invention concerne un capteur d'images (1) comprenant des cellules photosensibles (B, G, R), chaque cellule photosensible comportant au moins un moyen de stockage de charges (11R, 11G, 11B) formé au moins en partie dans un substrat (9) d'un matériau semiconducteur. Le substrat comprend, pour au moins une première cellule photosensible (B), une portion (10B) d'un premier alliage de silicium et de germanium ayant une première concentration de germanium (XB), éventuellement nulle, et pour au moins une deuxième cellule photosensible (G, R), une portion (10G, 10R) d'un deuxième alliage de silicium et de germanium ayant une deuxième concentration de germanium (XG, XR), non nulle, strictement supérieure à la première concentration de germanium.

公开(公告)号：FR2905519B1

公开(公告)日：2008-12-19

申请号：FR0653524

申请日：2006-08-31

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： CORONEL PHILIPPE ,  MARTY MICHEL

IPC: H01L21/8236 ,  H01L27/088

Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

公开(公告)号：FR2838866B1

公开(公告)日：2005-06-24

申请号：FR0205073

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/68 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/40 ,  H01L21/70 ,  H01L27/108

Abstract: Fabrication of an integrated electronic component comprises: producing an initial structure (SI) incorporating volumes of respective materials forming a definite pattern (M) on a first substrate; transferring the pattern to a second substrate (200); and producing, on the second substrate surface, an additional structure by using the volumes of the materials of the pattern as alignment markers. Fabrication of an integrated electronic component comprises: (a) producing, on the surface of a first substrate (100), an initial structure (SI) incorporating volumes of respective materials, at least part of the volumes forming a definite pattern (M); (b) transferring at least a part of the initial structure (SI) comprising the pattern of the first substrate (100) to a second substrate (200); and (c) producing, on the surface of the second substrate (200), an additional structure by using at least some of the volumes of the materials of the pattern (M) as alignment markers. Independent claims are given for: (i) an integrated electronic component obtained by the invented process; and (ii) an electronic device comprising a transistor, or a diode, or a dynamic random access memory (DRAM) element.

公开(公告)号：FR2838238B1

公开(公告)日：2005-04-15

申请号：FR0204358

申请日：2002-04-08

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

IPC: H01L21/336 ,  H01L29/786

Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

公开(公告)号：FR2830984B1

公开(公告)日：2005-02-25

申请号：FR0113375

申请日：2001-10-17

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE ,  TORRES JOAQUIM

IPC: H01L21/762 ,  H01L21/764

公开(公告)号：FR2845201A1

公开(公告)日：2004-04-02

申请号：FR0211989

申请日：2002-09-27

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/336 ,  H01L21/28

Abstract: The formation of a portion of a composite material from the elements of an initial material and a metal at the heart of an electronic circuit, comprises: (a) formation of a cavity (C) incorporating at least one opening (O) towards an access surface and presenting an internal wall having a zone of an initial material; (b) deposition of a metal (6) in the proximity of this zone of initial material; (c) heating of the circuit to form a portion of composite material (26) in the zone of initial material; (d) withdrawing from the cavity, via the opening, at least one portion of the metal not having formed the composite material. Independent claims are also included for: (a) an electronic circuit incorporating a portion of composite material formed by this method and acting as an electrical connection; (b) a MOS transistor incorporating a gate having a portion of composite material formed by this method.

公开(公告)号：FR2844395A1

公开(公告)日：2004-03-12

申请号：FR0211054

申请日：2002-09-06

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CORONEL PHILIPPE ,  TAVEL BRICE ,  SKOTNICKI THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The production of an electronic component consists of: (a) covering the surface (S) of a substrate (100) with a portion (P) delimiting with the substrate a volume (V) filled at least partially with a temporary material; (b) evacuating the temporary material from the volume by a shaft (C) extending between the volume and an access surface; (c) introducing an electrical conducting filling material (7) into the volume from some precursors fed via the shaft. Independent claims are also included for: (1) a field effect transistor with a gate produced by this method; (2) an electronic device incorporating such a transistor.

公开(公告)号：FR2842944A1

公开(公告)日：2004-01-30

申请号：FR0209347

申请日：2002-07-23

Applicant: ST MICROELECTRONICS SA

Inventor： FERREIRA PAUL ,  CORONEL PHILIPPE

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/60 ,  H01L23/50 ,  H01L21/265

Abstract: The method for making contact openings in the upper surface of an integrated circuit in regions between higher zones applies in two cases, when the higher zones are well-spaced with noncritical openings (41), and when the higher zones are in proximity with critical openings (42). The method comprises the steps of covering the upper surface structure with a first protection layer (20); making the noncritical openings (41) in the first protection layer; covering the structure with the secodn protection layer; oblique irradiation carried out so that the second protection layer is not irradiated at the bottom of regions between two higher zones; eliminating the nonirradiated parts of the second protection layer; eliminating the parts of the first protection layer at locations where the second protection layer has been eliminated; and eliminating the irradiated parts of the second protection layer. The first protection layer (20) is of silicon nitride. The second protection layer is of polycrystalline silicon. The irradiation process is that of boron implanting. The oblique irradiation is carried out at an angle in the range 45-60 deg. The higher zones correspond to the gates (3) of MOS transistors. The zones susceptible of contact, that is a short-circuit, are covered with a metal silicide. The step of making the noncritical openings (41) comprises the steps of covering the structure with a planarization layer; eliminating the planarization layer at locations of the openings; etching the openings in the first protection layer; and eliminating the planarization layer. The planarization layer is of resin.