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公开(公告)号：KR100938675B1
公开(公告)日：2010-01-25
申请号：KR1020070132724
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: 본 발명은 박막 트랜지스터의 소스-드레인 전류 모델링 방법에 관한 것으로, 본 발명의 일실시 예에 따른 박막 트랜지스터의 소스-드레인 전류 모델링 방법은, 표본 입력 값 및 표본 출력 값을 포함하는 표본 데이터를 입력받는 단계; 상기 표본 데이터에 상응하여 모델링 변수를 조정하는 단계; 상기 조정된 모델링 변수에 상응하여 전류 모델 값을 계산하는 단계; 상기 계산된 전류 모델 값과 상기 표본 출력 값의 차이 값이 미리 설정된 기준 값보다 작은 경우에는 상기 조정된 모델링 변수를 전류 모델에 적용하여 전류 모델을 피팅(fitting)하는 단계; 상기 피팅된 전류 모델에 실제 입력 데이터를 입력하는 단계; 및 상기 실제 입력 데이터에 상응하여 결과치를 출력하는 단계를 포함하되, 상기 전류 모델은 식(I
DS = I
leak + ( 1/I
b + 1/I
a )
-1 )에 의하여 드레인-소스 전류(I
DS )를 계산한다. 여기서, I
leak 는 박막 트랜지스터의 누설 전류, I
b 는 문턱 전압(threshold voltage) 이하의 영역에서 계산되는 소스-드레인 전류 값인 제 1 전류 값, I
a 는 문턱 전압 이상의 영역에서 계산되는 소스-드레인 전류 값인 제 2 전류 값이다.
상기와 같은 본 발명에 의하면, 산화물 TFT 뿐만 아니라 비결정질 실리콘 TFT 및 유기 TFT 에도 적용될 수 있는 정밀한 전류 모델을 제공할 수 있는 이점이 있다.
TFT 모델, 드레인-소스 전류, 산화물 TFT-
公开(公告)号：KR1020100006519A
公开(公告)日：2010-01-19
申请号：KR1020080071163
申请日：2008-07-22
Applicant: 한국전자통신연구원
IPC: C04B35/00 , H01B1/08 , H01L21/336 , H01L29/78
CPC classification number: C04B35/00 , H01B1/08 , H01L21/02554 , H01L21/02565 , H01L29/78693
Abstract: PURPOSE: An oxide semiconductor thin film composition is provided to obtain stable and transparent oxide semiconductor thin film having high mobility through low temperature process. CONSTITUTION: An oxide semiconductor thin film composition is amorphous state containing aluminum-containing oxide, zinc-containing oxide, indium-containing oxide, and tin-containing oxide. The ratio of the metal components is 30-95at% of zinc, 1-65at% of indium, 1-50at% of tin and remaining amount of aluminum.
Abstract translation: 目的：提供氧化物半导体薄膜组合物以获得通过低温处理具有高迁移率的稳定且透明的氧化物半导体薄膜。 构成：氧化物半导体薄膜组合物是含有含氧氧化物，含锌氧化物，含铟氧化物和含锡氧化物的非晶态。 金属成分的比例为锌的30-95原子％，铟的1-65原子％，锡的1-50原子％和铝的剩余量。
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公开(公告)号：KR1020090099140A
公开(公告)日：2009-09-22
申请号：KR1020080024208
申请日：2008-03-17
Applicant: 한국전자통신연구원
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L21/02554
Abstract: A manufacturing method of a ZnO TFT is provided to reduce a defect inside a semiconductor thin film by controlling a deposition temperature after selecting oxygen plasma or ozone as oxygen precursor. A ZnO semiconductor film(30) is formed on a substrate(10) through an atomic layer deposition method using Zn precursor and ozone at a temperature of 250~350°C or Zn precursor and oxygen plasma at a temperature of 150~250°C. An insulation film(40) is formed on a top part of the ZnO semiconductor film through the atomic layer deposition method using the oxygen precursor selected from ozone or water at a temperature less than 250°C. A gate electrode(50) is formed on a top part of the insulation film. The ZnO semiconductor film has thickness of 5~40nm. The substrate is a substrate in which a source/drain electrode(20) is formed and a substrate in which the gate electrode and the insulation film are formed.
Abstract translation: 提供ZnO薄膜晶体管的制造方法，通过在选择氧等离子体或臭氧作为氧前体后控制沉积温度来减少半导体薄膜内的缺陷。 在250〜350℃的温度下，使用Zn前体和臭氧，在150〜250℃的温度下，通过Zn前体和氧等离子体，通过原子层沉积法在基板（10）上形成ZnO半导体膜（30） 。 通过使用在低于250℃的温度下使用选自臭氧或水的氧前体的原子层沉积方法，在ZnO半导体膜的顶部上形成绝缘膜（40）。 在绝缘膜的顶部形成有栅电极（50）。 ZnO半导体膜的厚度为5〜40nm。 基板是形成源极/漏极（20）的基板和形成有栅电极和绝缘膜的基板。
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公开(公告)号：KR100833489B1
公开(公告)日：2008-05-29
申请号：KR1020060016665
申请日：2006-02-21
Applicant: 한국전자통신연구원
CPC classification number: H01L33/34 , B82Y20/00 , H01L33/18 , Y10S438/962 , Y10S977/773 , Y10S977/774
Abstract: 본 발명은 빛을 발산하는 발광층, 상기 발광층에 형성된 정공 주입층, 상기 정공 주입층과 대향되도록 상기 발광층에 형성된 전자 주입층, 상기 전자 주입층에 형성된 금속 나노 점(nano dot)을 포함하는 금속층, 및 상기 금속층에 형성된 투명 전도성 전극을 포함하는 실리콘 나노 점을 이용한 반도체 발광 소자 및 이의 제조 방법을 개시한다. 상기 발광층으로 실리콘 나노 점을 포함하는 비정질의 실리콘 나이트라이드를 포함한다.
실리콘 나노 점, 반도체 발광 소자, 금속층, 투명 전도성 전극-
公开(公告)号：KR100586178B1
公开(公告)日：2006-06-07
申请号：KR1020030097061
申请日：2003-12-26
Applicant: 한국전자통신연구원
IPC: H01L27/08 , H01L27/12 , H01L31/108
CPC classification number: H01L29/47
Abstract: 본 발명은 SOI 기판을 이용한 쇼트키 장벽 관통 트랜지스터 및 그 제조방법으로, 종래의 불순물을 주입하여 소스 및 드래인 영역을 구성하는 방식의 전계효과 트랜지스터 대신에 소스 및 드레인을 실리콘과 금속의 반응 물질인 실리사이드로 대체하여 금속-반도체간에 형성되는 쇼트키 장벽을 이용하여 제작하는 쇼트키 장벽 관통 트랜지스터를 제공한다.
쇼트키, SOI, 실리사이드, MOSFET-
Patent Agency Ranking
公开(公告)号：KR100460839B1
公开(公告)日：2004-12-09
申请号：KR1020020002534
申请日：2002-01-16
Applicant: 한국전자통신연구원
IPC: H01S5/183
Abstract: PURPOSE: A multi-channel long wavelength VCSEL array and a fabricating method thereof are provided to form constantly an interval of a laser oscillation wavelength by controlling a resonant interval. CONSTITUTION: A multi-channel long wavelength VCSEL array includes a semiconductor substrate(10), a bottom mirror(20), an active region(30), a current limit layer(40), a superlattice control layer(50), and a top mirror(60). The bottom mirror is formed on the semiconductor substrate. The active region is formed on the bottom mirror. The current limit layer is formed on the active region in order to limit efficiently the current and enhance the efficiency of the heat transfer. The superlattice control layer is formed on the current limit layer in order to control an interval of laser oscillation wavelength. The top mirror is formed on the superlattice control layer.
Abstract translation: 目的：提供多通道长波长VCSEL阵列及其制造方法，以通过控制谐振间隔恒定地形成激光振荡波长的间隔。 一种多通道长波长VCSEL阵列，包括半导体衬底（10），底部反射镜（20），有源区（30），限流层（40），超晶格控制层（50）和 顶部镜子（60）。 底部反射镜形成在半导体衬底上。 有源区形成在底部反射镜上。 电流限制层形成在有源区域上，以便有效地限制电流并提高传热效率。 在限流层上形成超晶格控制层，以控制激光振荡波长的间隔。 顶部镜子形成在超晶格控制层上。
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公开(公告)号：KR1020040041732A
公开(公告)日：2004-05-20
申请号：KR1020020069588
申请日：2002-11-11
Applicant: 한국전자통신연구원
IPC: H01S5/183
CPC classification number: H01S5/18305 , H01S5/0422 , H01S5/125
Abstract: PURPOSE: A long wavelength vertical cavity surface emitting laser(VCSEL) and a method for manufacturing the same are provided to improve the current confinement structure by introducing a tunnel junction layer, a low energy ion injection and a heat spreading layer. CONSTITUTION: A long wavelength vertical cavity surface emitting laser(VCSEL) includes a laser active layer(30) and a current confinement structure(C). The current confinement structure(C) is provided with a barrier layer(40), a tunnel junction layer(50), a heat spread layer(60) and an electric insulation layer(70). The barrier layer(40) is formed on the laser active layer(30). The tunnel junction layer(50) is formed on the barrier layer(40) with stacking p-type and n-type materials alternatively. The heat spread layer(60) is formed on the tunnel junction layer(50). And, the electric insulation layer(70) is formed by using a low energy ion implantation method to electrically insulate the tunnel junction layer(50).
Abstract translation: 目的：提供长波长垂直腔面发射激光器（VCSEL）及其制造方法，以通过引入隧道结层，低能离子注入和散热层来改善电流限制结构。 构成：长波长垂直腔表面发射激光器（VCSEL）包括激光有源层（30）和电流限制结构（C）。 电流限制结构（C）设置有阻挡层（40），隧道结层（50），散热层（60）和电绝缘层（70）。 阻挡层（40）形成在激光活性层（30）上。 交替地堆叠p型和n型材料，在势垒层（40）上形成隧道结层（50）。 扩散层（60）形成在隧道结层（50）上。 并且，通过使用低能离子注入方法来形成电绝缘层（70）以使隧道结层（50）电绝缘。
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公开(公告)号：KR1020040041730A
公开(公告)日：2004-05-20
申请号：KR1020020069586
申请日：2002-11-11
Applicant: 한국전자통신연구원
IPC: H01S5/30
CPC classification number: H01L33/145 , H01S5/18308 , H01S5/18316 , H01S5/18347 , H01S5/3095 , H01S2301/176
Abstract: PURPOSE: A semiconductor optical device provided with a current confined structure is provided to secure the reliability by reducing the leakage current at the etched surface with filling an oxide layer or a nitride layer. CONSTITUTION: A semiconductor optical device provided with a current confined structure includes a semiconductor substrate(10), a first semiconductor layer(12), a second semiconductor layer(14), a third semiconductor layer(16). The first semiconductor layer(12) is formed on the semiconductor substrate(10) and made of at least one first conductive type of material. The second semiconductor layer(14) is formed on the first semiconductor layer(12) and is made of at least one material. The third semiconductor layer(16) is formed on the second semiconductor layer(16) and is made of at least one second conductive type of material which is opposite to the first conductive type. The first to third semiconductor layers(12,14,16) form the mesa structure, the side surface of at least one material layer constituting the first to third semiconductor layers(12,14,16) is recessed and the recessed portion is filled with oxide layer or a nitride layer, partially or totally.
Abstract translation: 目的：提供一种具有电流限制结构的半导体光学器件，以通过减少在蚀刻表面处的填充氧化物层或氮化物层的漏电流来确保可靠性。 构成：设置有电流限制结构的半导体光学器件包括半导体衬底（10），第一半导体层（12），第二半导体层（14），第三半导体层（16）。 第一半导体层（12）形成在半导体衬底（10）上并由至少一种第一导电类型的材料制成。 第二半导体层（14）形成在第一半导体层（12）上并且由至少一种材料制成。 第三半导体层（16）形成在第二半导体层（16）上并且由与第一导电类型相反的至少一种第二导电类型的材料制成。 第一至第三半导体层（12,14,16）形成台面结构，构成第一至第三半导体层（12,14,16）的至少一个材料层的侧表面是凹进的，并且凹陷部分填充有 氧化物层或氮化物层，部分或全部。
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公开(公告)号：KR1020030074937A
公开(公告)日：2003-09-22
申请号：KR1020020013936
申请日：2002-03-14
Applicant: 한국전자통신연구원
IPC: H01S5/183
Abstract: PURPOSE: A method for fabricating an intracavity-contacted VCSEL including selective upper mirror layer growth is provided to simplify a heat emission path and a current injection path by using a selective region growth method. CONSTITUTION: A lower mirror layer(200), a laser resonance layer(300), a current injection hole forming layer, and an intracavity-contacted layer are sequentially grown on a substrate(100). An intracavity-contacted layer pattern(500) is formed by wet-etching the current injection hole forming layer. A mask pattern(600) is formed on the intracavity-contacted layer pattern(500). An upper mirror layer(250) is formed on an upper surface of the intracavity-contacted layer pattern(500). The first electrode(700) is formed on the intracavity-contacted layer pattern(500). The second electrode(750) is formed on a back surface of the substrate(100).
Abstract translation: 目的：提供一种用于制造包括选择性上镜层生长的腔内接触VCSEL的方法，以通过使用选择性区域生长方法简化热发射路径和电流注入路径。 构成：在基板（100）上依次生长下镜面（200），激光谐振层（300），电流注入孔形成层和腔内接触层。 通过湿蚀刻电流注入孔形成层形成腔内接触层图案（500）。 在腔内接触层图案（500）上形成掩模图案（600）。 在腔内接触层图案（500）的上表面上形成上镜层（250）。 第一电极（700）形成在腔内接触层图案（500）上。 第二电极（750）形成在基板（100）的背面上。
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公开(公告)号：KR1020030038072A
公开(公告)日：2003-05-16
申请号：KR1020010069489
申请日：2001-11-08
Applicant: 한국전자통신연구원
IPC: H01S5/183
CPC classification number: B82Y20/00 , H01S5/18311 , H01S5/18341 , H01S5/18344 , H01S5/34306 , H01S5/34313 , H01S5/3434
Abstract: PURPOSE: A VCSEL(Vertical-Cavity Surface Emitting Laser) for long wavelength having a current caliber of an oxide layer is provided to minimize the loss of the current and the charges by using the InAlAs oxide layer for restraining the InAlAs current path layer. CONSTITUTION: An n-type lower mirror layer(120) and an active layer(130) are sequentially formed on an n-type InP substrate(110). The n-type lower mirror layer(120) satisfies a Bragg reflection condition. A current path layer(142) and a current limit layer(144) are formed on a part of the active layer(130). The current path layer(142) is surrounded by the current limit layer(144). A p-type internal resonance contact layer(150) is formed on the current path layer(142) and the current limit layer(144). An upper mirror layer(160) is formed on a part of the p-type internal resonance contact layer(150). A p-type electrode(170) is formed on the p-type internal resonance contact layer(150) and the upper mirror layer(160). An n-type electrode(180) is formed on a part of a back side of the n-type InP substrate(110).
Abstract translation: 目的：提供具有电流口径为氧化物层的长波长VCSEL（垂直腔表面发射激光器），以通过使用InAlAs氧化物层来抑制InAlAs电流通路层来最小化电流损耗和电荷。 构成：在n型InP衬底（110）上依次形成n型下镜层（120）和有源层（130）。 n型下镜层（120）满足布拉格反射条件。 在有源层（130）的一部分上形成电流通路层（142）和限流层（144）。 电流通路层142由电流极限层144包围。 在电流通路层（142）和限流层（144）上形成p型内部共振接触层（150）。 在p型内部共振接触层（150）的一部分上形成上镜层（160）。 p型电极（170）形成在p型内部共振接触层（150）和上镜层（160）上。 n型电极（180）形成在n型InP衬底（110）的背侧的一部分上。
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