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公开(公告)号：KR1020030042791A
公开(公告)日：2003-06-02
申请号：KR1020010073570
申请日：2001-11-24
Applicant: 한국전자통신연구원
IPC: G02B6/42
CPC classification number: G02B6/4201 , G02B6/4274 , G02B6/4279 , H01L2224/48091 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A sub mount for photoelectric module and a mounting method using the same are provided to enhance an electrical characteristic by using a signal connection line of a co-planar waveguide structure. CONSTITUTION: A sub mount(200) for converting an incident ray of a photoelectric element(230) to an electric signal includes a dielectric(210) and a signal connection line(220). The dielectric has a front side(211) and a bottom side(212). The signal connection line is adhered on the front side and the bottom side. The signal connection line is electrically connected with the photoelectric element in order to output the electric signal from the photoelectric element. The signal connection line having a co-planar waveguide structure includes a plurality of signal connection lines. The plural signal connection lines include the first ground line(221), a signal transmission line(222), the second ground line(223), and a bias application line(224).
Abstract translation: 目的：提供一种用于光电模块的辅助安装座及其安装方法，以通过使用共面波导结构的信号连接线来增强电气特性。 构成：用于将光电元件（230）的入射光线转换为电信号的副安装座（200）包括电介质（210）和信号连接线（220）。 电介质具有前侧（211）和底侧（212）。 信号连接线粘附在前侧和底侧。 信号连接线与光电元件电连接，以便从光电元件输出电信号。 具有共平面波导结构的信号连接线包括多个信号连接线。 多个信号连接线包括第一接地线（221），信号传输线（222），第二接地线（223）和偏置施加线（224）。
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公开(公告)号：KR100385856B1
公开(公告)日：2003-06-02
申请号：KR1020000082810
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L21/335
CPC classification number: H01L29/66848
Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.
Abstract translation: 本发明提供了一种自对准栅极晶体管。 本发明仅在具有离子注入沟道层的半导体衬底上的栅极下方的沟道区下方以及源极和漏极下方的P型杂质离子注入P型杂质离子，而不将P型杂质离子注入到源极栅极 和栅极 - 漏极，沉积栅极金属并蚀刻栅极图案。 在这种情况下，栅极的长度（Lg）被限定为比在沟道层下方注入P型杂质离子的长度（Lch-g）窄，因此改善了夹断特性。 根据本发明的制造具有自对准栅极的场效应晶体管的方法包括以下步骤：仅在栅极下面的沟道区下面以及源极和漏极下面注入P型杂质离子; 以及使用干蚀刻方法沉积具有良好高温稳定性的耐火栅极金属以形成栅极图案。
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公开(公告)号：KR1020030013580A
公开(公告)日：2003-02-15
申请号：KR1020010047655
申请日：2001-08-08
Applicant: 한국전자통신연구원
IPC: H01L31/12
Abstract: PURPOSE: A photodetector is provided to minimize a tunneling leakage current and improve the capability of a light receiving chip in which the photodetector and a hetero-junction bipolar transistor are integrated into a single chip, by smoothly transferring the charges generated in a light absorbing layer. CONSTITUTION: The first conductive layer of the first conductivity type is formed in a predetermined region on a substrate(40). A light absorbing layer(43) is stacked on the first conductive layer. The second conductive layer of the second conductivity type is stacked on the light absorbing layer. The third conductive layer are formed between the first conductive layer and the light absorbing layer and between the light absorbing layer and the second conductive layer, decreasing a lattice match and a potential energy band difference between the two stack layers to make photoelectrons flow smoothly.
Abstract translation: 目的：提供一种光电检测器，以最小化隧道泄漏电流，并通过平滑地转移在光吸收层中产生的电荷，提高光接收芯片和异质结双极晶体管集成到单个芯片中的光接收芯片的能力 。 构成：第一导电类型的第一导电层形成在衬底（40）上的预定区域中。 光吸收层（43）层叠在第一导电层上。 第二导电类型的第二导电层堆叠在光吸收层上。 第三导电层形成在第一导电层和光吸收层之间，并且在光吸收层和第二导电层之间，减小了两个堆叠层之间的晶格匹配和势能带差，使得光电子流畅地流动。
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公开(公告)号：KR100311740B1
公开(公告)日：2001-10-12
申请号：KR1019990054279
申请日：1999-12-01
Applicant: 한국전자통신연구원
IPC: H01L21/306
Abstract: 본발명은 III족질화물(Group III-nitrides)의식각방법에있어서기존의방법으로식각되지않는 p-형의기판을식각할수 있도록하고식각의효율을개선한에너지대구부러짐을이용한반도체의광전화학적식각방법에관한것이다. 본발명은 III족질화물의기판에저항성접촉을형성한뒤 역바어스전압을인가하여식각용액과접촉된반도체기판표면에홀(hole)의전위우물을형성하여파장이짧은빛의조사에의해생성된홀이기판의표면에축적되도록하므로써기판의산화에기여하도록하여식각효율을높인다. 따라서본 발명은 p-GaN 의식각을가능하게할 뿐아니라 n-GaN 의식각율을높일수 있으며, 역바이어스전압을변화시킴으로써식각속도를조절할수 있다.
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公开(公告)号：KR1020010048979A
公开(公告)日：2001-06-15
申请号：KR1019990053886
申请日：1999-11-30
Applicant: 한국전자통신연구원
IPC: H01L29/78
Abstract: PURPOSE: A method for manufacturing a field effect transistor is provided to efficiently radiate a lot of quantity of heat generated in a channel layer, and to reduce parasitic inductance by a bonding wire. CONSTITUTION: A channel layer is formed on a semiconductor substrate. A source electrode, a drain electrode and a gate electrode are formed on the channel layer. An insulating layer is formed on the channel layer, the source electrode, the drain electrode and the gate electrode. A bump composed of a conductive material is formed on the source electrode so that a part of the bump is buried in the insulating layer and the rest of the bump is protruded from the insulating layer.
Abstract translation: 目的：提供一种用于制造场效应晶体管的方法，以有效地辐射在沟道层中产生的大量热量，并且通过接合线来减少寄生电感。 构成：在半导体衬底上形成沟道层。 在沟道层上形成源电极，漏电极和栅电极。 在沟道层，源电极，漏电极和栅电极上形成绝缘层。 在源电极上形成由导电材料构成的凸块，使得凸块的一部分埋在绝缘层中，其余的凸块从绝缘层突出。
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Patent Agency Ranking
公开(公告)号：KR102219400B1
公开(公告)日：2021-02-26
申请号：KR1020150120212
申请日：2015-08-26
Applicant: 한국전자통신연구원
Abstract: 반도체채널저항의등가회로를구성하는방법은, 반도체채널저항의제 1 전극및 제 2 전극을정의하는단계, 상기제 1 전극및 상기제 2 전극사이에연결되는수동소자부를정의하는단계및 상기수동소자부내 상기적어도두 개의수동소자의파라미터값을각각결정하는단계를포함한다. 여기에서, 상기수동소자부는병렬연결된적어도두 개의수동소자를포함한다. 따라서, 주파수변화에도불구하고반도체채널저항의특성을정확히나타낼수 있다.
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公开(公告)号：KR101848244B1
公开(公告)日：2018-05-29
申请号：KR1020110133715
申请日：2011-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
CPC classification number: H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: 본발명은계단형게이트전극을포함하는반도체소자및 그제조방법에관한것이다. 본발명의일 실시예에의한반도체소자의제조방법은, 다수의에피택셜층(epitaxial layer) 구조의반도체기판상에캡층(cap layer)을형성하고상기캡층의일부를식각하여활성영역을형성하는단계, 상기활성영역과상기캡층상에제 1 질화막, 제 2 질화막및 게이트형성을위한레지스트패턴을순차적으로형성하는단계, 상기레지스트패턴을통해상기제 2 질화막과상기제 1 질화막을순차적으로식각하고상기레지스트패턴을제거하여계단형의게이트절연막패턴을형성하는단계, 상기제 2 질화막상에게이트헤드패턴을형성하는단계, 상기게이트절연막패턴을통해상기반도체기판최상부의쇼트키층일부를식각하여언더컷(under-cut) 영역을형성하는단계, 상기게이트절연막패턴과상기게이트헤드패턴을통해내열성금속을증착하여계단형의게이트전극을형성하는단계및 상기게이트헤드패턴을제거하고절연막을증착하는단계를포함한다.
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公开(公告)号：KR101857214B1
公开(公告)日：2018-05-14
申请号：KR1020110139142
申请日：2011-12-21
Applicant: 한국전자통신연구원
IPC: H04B1/06
Abstract: 본발명은하나의기판에다채널안테나를포함하는빔스캔수신기를구현함으로써면적을줄이고제작비용을절감할수 있는다채널빔스캔수신기에관한것이다. 본발명의일 실시예에의한다채널빔스캔수신기는, 다채널안테나, 상기다채널안테나를통해수신한다수의신호중 하나를선택하는스위치, 상기스위치에서선택된신호를 1차증폭하는제 1 저잡음증폭기, 상기 1차증폭된신호를필터링(filtering)하는대역통과필터, 상기필터링된신호를 2차증폭하는제 2 저잡음증폭기및 상기 2차증폭된신호를전압으로변환하는검출기를포함한다.
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