公开(公告)号：IT1316002B1

公开(公告)日：2003-03-26

申请号：ITRM20000577

申请日：2000-11-08

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MOTTA ILARIA ,  MICHELONI RINO ,  TORELLI GUIDO

IPC: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

公开(公告)号：DE69901259D1

公开(公告)日：2002-05-16

申请号：DE69901259

申请日：1999-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  PIERIN ANDREA ,  TORELLI GUIDO

IPC: G11C16/06 ,  G11C5/14

Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

公开(公告)号：ITTO20000892A1

公开(公告)日：2002-03-22

申请号：ITTO20000892

申请日：2000-09-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

公开(公告)号：IT1311441B1

公开(公告)日：2002-03-12

申请号：ITTO990994

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

公开(公告)号：IT1311440B1

公开(公告)日：2002-03-12

申请号：ITTO990993

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/30

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

公开(公告)号：ITMI20001585A1

公开(公告)日：2002-01-14

申请号：ITMI20001585

申请日：2000-07-13

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  SANGALLI MIRIAM

IPC: G11C16/08

公开(公告)号：DE69232170D1

公开(公告)日：2001-12-06

申请号：DE69232170

申请日：1992-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

公开(公告)号：ITTO990993A1

公开(公告)日：2001-05-16

申请号：ITTO990993

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/30

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

公开(公告)号：DE69516402T2

公开(公告)日：2000-11-02

申请号：DE69516402

申请日：1995-07-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

IPC: G11C11/56

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

公开(公告)号：DE69514783T2

公开(公告)日：2000-06-08

申请号：DE69514783

申请日：1995-03-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).