公开(公告)号：WO2008054946A1

公开(公告)日：2008-05-08

申请号：PCT/US2007/080164

申请日：2007-10-02

Applicant: RAYTHEON COMPANY ,  CHAHAL, Premjeet ,  ABLES, Billy, D. ,  RAJENDRAN, Sankerlingam ,  MORRIS, Francis, J.

Inventor： CHAHAL, Premjeet ,  ABLES, Billy, D. ,  RAJENDRAN, Sankerlingam ,  MORRIS, Francis, J.

IPC: H01L21/768

CPC classification number: H05K3/3457 ,  H01L21/486 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09572 ,  H05K2201/10666 ,  H05K2201/2081 ,  H05K2203/0278 ,  H05K2203/043 ,  H01L2924/00

Abstract: According to one embodiment of the invention, a method for sealing one or more vias comprises providing a first substrate having vias, forming an adhesion layer on an inner surface of the vias, sandwiching a solder layer between the first substrate and a second substrate, and elevating of the first substrate, second substrate, and solder layer to a temperature above a eutectic point and below a melting point of the solder layer. The act of elevating the solder layer to a temperature above the eutectic point and below the melting point causes the solder layer to flow into the vias in a generally consistent manner.

Abstract translation: 根据本发明的一个实施例，用于密封一个或多个通孔的方法包括提供具有通孔的第一基板，在通孔的内表面上形成粘合层，将焊料层夹在第一基板和第二基板之间，以及 将第一基板，第二基板和焊料层升高到高于共晶点且低于焊料层的熔点的温度。 将焊料层升高到高于共熔点并低于熔点的温度的作用导致焊料层以大致一致的方式流入通孔。

公开(公告)号：WO2006039653A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/035488

申请日：2005-09-30

Applicant: TERADYNE, INC. ,  BEHZIZ, Arash ,  BREINLINGER, Keith ,  EVANS, David ,  PARRISH, Frank

Inventor： BEHZIZ, Arash ,  BREINLINGER, Keith ,  EVANS, David ,  PARRISH, Frank

IPC: G01R31/28

CPC classification number: H05K1/0243 ,  G01R31/2889 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/09809 ,  H05K2201/10356 ,  H05K2201/10666

Abstract: In one embodiment, a tester interface module (10) for connecting a plurality of signal paths from at least one electronic assembly to at least one other electronic assembly is provided. The interface module includes a capture board (150) having center conductor vias (172) with center conductor holes (170) extending through the capture board. Axial cables (110) secured to the capture board have center conductors (160) extending at least part way through a corresponding center conductor hole of the center conductor via. An interface component (200) is adjacent to the capture board, the conductor paths being conductively bonded to the conductor vias of the capture board so as to electrically connect center conductors to corresponding conductor paths. The conductor paths of the interface component are arranged to allow connection with an electronic assembly.

Abstract translation: 在一个实施例中，提供了一种用于将多个信号路径从至少一个电子组件连接到至少一个其它电子组件的测试器接口模块（10）。 接口模块包括具有中心导体通孔（172）的捕获板（150），中心导体孔（172）具有延伸穿过捕获板的中心导体孔（170）。 固定到捕获板的轴向电缆（110）具有至少部分延伸穿过中心导体通孔的相应中心导体孔的中心导体（160）。 接口部件（200）与捕获板相邻，导体路径导电地接合到捕获板的导体通孔，以将中心导体电连接到相应的导体路径。 接口部件的导体路径被布置成允许与电子组件的连接。

公开(公告)号：WO02067644A9

公开(公告)日：2004-05-13

申请号：PCT/IT0100083

申请日：2001-02-21

Applicant: CANDORE AMEDEO

Inventor： CANDORE AMEDEO

IPC: B23K37/04 ,  H05K3/46

CPC classification number: B23K37/0408 ,  B23K2201/42 ,  B32B38/1841 ,  B32B2457/08 ,  H05K3/4614 ,  H05K3/4638 ,  H05K2201/09781 ,  H05K2201/10666 ,  H05K2203/167

Abstract: A method of fabricating a multilayer printed circuit board, comprises alternately stacking on a template (1) having at least two vertical alignment pins (2), predefined printed circuit sub-boards (3) and pre-impregnated sheets (12) precursors of dielectric layers of reinforced resin between said sub-boards, all provided with alignment holes (14, 5), binding together the components of the assembled stack, lifting the stack off the alignment pins (2), transferring it between the platens of a press and hot pressing it causing polymerization of the resin of said pre-impregnated sheets. The method consists in defining at least a pair of soldering pads (7) with hole therethrough at certain positions relative to said alignment holes (14, 5) on both faces of each of said sub-boards (3) except the lowermost sub-board on which blind pads (6) are defined on at least its upper face; indenting or perforating each pre-impregnated sheet (12) such not to overlap said pads (6, 7) and soldering each newly stacked sub-board (3) to the previously stacked underlying sub-board (3) through the respective pads (7) with a hole therethrough. The machine employs a template (1) having at least two vertical alignment pins (2); a least two electric soldering irons (16), soldering each sub-board (3) just stacked to the previously stacked underlying one through welding pads (7) having a hole therethrough and has means (18) for moving each one of said soldering irons along three orthogonal axis onto a respective one of said pads (7) with a hole therethrough to make the soldering, and off and away from the stack when the soldering have been done.

Abstract translation: 一种制造多层印刷电路板的方法，包括交替地堆叠在具有至少两个垂直对准销（2），预定印刷电路子板（3）和预浸渍片（12）的模板（1）上，所述预浸渍片（12） 在所述子板之间的增强树脂层，均设有对准孔（14,5），将组装好的堆叠的部件结合在一起，将堆叠从对准销（2）上提起，将其转移到压力机的压板和 热压它导致所述预浸渍片材的树脂聚合。 该方法包括在每个所述子板（3）的两个面上的相对于所述对准孔（15）的某些位置处至少限定一对具有孔的焊盘（7），除了最下面的子板 至少在其上表面上限定了盲垫（6）; 每个预浸渍片材（12）的凹陷或穿孔，使得不与所述垫片（6,7）重叠，并且通过相应的垫片（7）将每个新堆叠的子板材（3）焊接到先前堆叠的下面的子板材（3） ）。 机器采用具有至少两个垂直对准销（2）的模板（1）; 至少两个电烙铁（16），通过具有穿过其中的孔的焊接垫（7）将每个子板（3）焊接到刚堆叠到先前堆叠的下层的子板上，并具有用于移动每个所述烙铁的装置（18） 沿着三个正交轴线到相应的一个所述焊盘（7）上，具有穿过其中的孔以进行焊接，并且在进行焊接时离开和离开堆叠。

公开(公告)号：WO01015504A1

公开(公告)日：2001-03-01

申请号：PCT/FR2000/002260

申请日：2000-08-07

IPC: G06K19/077 ,  H05K1/18 ,  H05K3/32

CPC classification number: G06K19/07769 ,  G06K19/077 ,  H01L2224/48091 ,  H01L2224/48228 ,  H05K1/183 ,  H05K3/321 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10719 ,  H05K2201/10727 ,  H01L2924/00014

Abstract: The invention concerns a method for making smart cards, said smart card comprising a card body (10) enclosing an antenna (20) at the ends of which are provided connection terminals (120) to be connected to an electronic module (20) housed in a cavity of said card body, the electronic module comprising on one surface at least an integrated circuit chip and on the other surface connection pads, the chip being connected to said pads. The method comprises steps which consist in: producing micro-perforations (213) passing through at least two contact pads (200) and if necessary the support of said pads; connecting the antenna (120) to said pads (200) by spraying electrically conductive material into the micro-perforations.

Abstract translation: 本发明涉及一种用于制造智能卡的方法，所述智能卡包括封闭天线（20）的卡体（10），其末端设有要连接到电子模块（20）的连接端子（120） 所述卡体的空腔，所述电子模块在至少一个集成电路芯片的一个表面上，在另一个表面上包括连接焊盘，所述芯片连接到所述焊盘。 该方法包括以下步骤：产生通过至少两个接触垫（200）的微穿孔（213），并且如果需要，产生所述垫的支撑; 通过将导电材料喷射到微穿孔中来将天线（120）连接到所述垫（200）。

公开(公告)号：WO1997042799A1

公开(公告)日：1997-11-13

申请号：PCT/GB1997001180

申请日：1997-05-01

Applicant: FORD MOTOR COMPANY ,  FORD MOTOR COMPANY LIMITED

Inventor： FORD MOTOR COMPANY ,  FORD MOTOR COMPANY LIMITED ,  TODD, Michael, George ,  SINKUNAS, Peter, Joseph ,  GLOVATSKY, Andrew, Zachary

IPC: H05K03/46

CPC classification number: H05K3/462 ,  H01L2924/1515 ,  H05K1/0284 ,  H05K1/119 ,  H05K1/144 ,  H05K3/368 ,  H05K3/4623 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/1059 ,  H05K2201/10666 ,  H05K2203/167 ,  Y10S438/977

Abstract: A three-dimensional multi-layer moulded electronic device and method for manufacturing same, wherein the device comprises at least two moulded, three-dimensional substrates (12, 14) having mating surfaces (20, 22), each substrate including a layer (16, 18) of patterned conductive material on at least one surface and electrically conductive vias (24, 26) at selected locations of the substrate for interconnection of the conductive layers (16, 18), wherein the substrates (20, 22) are electrically joined at their mating surfaces and the circuit layers (16, 18) are aligned and interconnected to form a multi-layer, three-dimensional circuit which may include moulded-in structural features.

Abstract translation: 一种三维多层成型电子器件及其制造方法，其中该器件包括具有配合表面（20,22）的至少两个模制的三维衬底（12,14），每个衬底包括一层（16 ，18）在至少一个表面上的图案化导电材料，以及在所述衬底的选定位置处的导电通孔（24,26），用于导电层（16,18）的互连，其中所述衬底（20,22）电连接 在它们的配合表面和电路层（16,18）被对准和互连以形成多层三维电路，其可以包括模制的结构特征。

公开(公告)号：WO1997034247A2

公开(公告)日：1997-09-18

申请号：PCT/EP1997001256

申请日：1997-03-12

Applicant: PAV CARD GMBH ,  WILM, Robert

Inventor： PAV CARD GMBH

IPC: G06K00/00

CPC classification number: G06K19/07728 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07779 ,  G06K19/07781 ,  G06K19/07783 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01077 ,  H05K1/0212 ,  H05K1/142 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0044 ,  H05K3/28 ,  H05K3/305 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/368 ,  H05K2201/0394 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2201/10818 ,  H05K2201/10977 ,  H05K2203/0228 ,  H05K2203/0285 ,  H05K2203/107 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: The invention concerns a smart card, a connection arrangement and a method of producing a smart card, a semiconductor chip located on a module being inserted into a recess (24) in a card carrier so as to be connected electrically and mechanically. According to a first feature of the invention, during the milling-out of the recess, a contact bump section is exposed (22, 23) such that a reliable connection is provided between the module and induction or antenna coil (11). According to a second and third feature, the required electrical contacts are produced by soldering and the required mechanical contacts are produced by heat-sealing or fusion adhesives. Furthermore, the adhesive is provided with conductive particles and is compressed when the connection is made, such that the necessary electrical contact is brought about. According to a fourth feature, a special reinforcement frame comprising insulating sections is provided. The reinforcement frame is used to increase mechanical stability and absorb torsion forces and stresses which can occur when the card is used. At the same time, the reinforcement frame permits easy contact with strip conductors inside the card, e.g. for inductive elements which form an antenna for contactless data-transmission.

Abstract translation: 本发明涉及一种芯片卡，连接器组件以及用于制造芯片卡，其特征在于，所述的上Hableiterchip在卡片托架的凹口（24）的模块用于获得电气和机械连接的方法。 根据本发明的第一方面，在研磨出凹槽，接触凸块的一部分露出（22，23），其使模块和感应或天线线圈（11）之间的安全连接。 根据由焊接和机械触点或通过热熔粘结剂必要的电触点的第二和第三个方面可以实现。 此外，粘合剂被在压力下的连接被压缩，从而形成所需的电接触被提出以提供粘合剂与导电性粒子。 根据本发明的第四方面，是提供了一种特殊的加强框架，其包括绝缘部分。 加强框架被用于增加机械稳定性和容纳可使用地图时发生扭转力和应力。 同时加强框架允许与位于卡互连内部接触的一个简单的方法，如 用于形成用于非接触式数据传输的天线的感应元件。

公开(公告)号：WO1997023123A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020080

申请日：1996-12-18

Applicant: INTEL CORPORATION ,  BARROW, Michael

Inventor： INTEL CORPORATION

IPC: H05K07/02

CPC classification number: H05K3/0094 ,  B23K1/0016 ,  B23K11/11 ,  B23K2101/40 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/114 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/1178 ,  H05K2203/1394 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: A ball grid array integrated circuit package (10) which has a plurality of vias (30) located within the solder pads (20) of a package substrate. The substrate supports an integrated circuit (24) which is connected to the solder pads (20) by the vias (30). Solder balls (36) used to solder the package (10) to an external printed circuit board (12) are attached to the solder pads (20) of the substrate. A solder mask plug (38) is formed within the vias (30) to prevent the solder balls (36) from wicking into the vias (30). Locating the vias (30) within the solder pads (20) optimizes the routing space of the substrate and increases the routing density of the package (10).

Abstract translation: 一种球栅阵列集成电路封装（10），其具有位于封装衬底的焊盘（20）内的多个通孔（30）。 衬底支撑通过通孔（30）连接到焊盘（20）的集成电路（24）。 用于将封装（10）焊接到外部印刷电路板（12）上的焊球（36）附接到基板的焊盘（20）。 在通孔（30）内形成有阻焊剂插塞（38），以防止焊球（36）吸入通孔（30）。 将焊盘（20）内的通路（30）定位可优化衬底的布线空间，并增加封装（10）的布线密度。

公开(公告)号：WO1993026146A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000148

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K07/20

CPC classification number: H05K7/205 ,  H05K1/0206 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: According to a process for producing a thermal layout, not only massive heat sinks are provided for absorbing heat, but also an optimized number of thermoconductive strips which distribute the heat over the printed circuit board. In the collecting zones are arranged higher capacity sinks into which the heat is transmitted. The thermoconductive strips may be thermoconductors (TL) provided for that purpose and more massive than the conductive strips for the electric connections, or conductive strips for electric connections, the electroconductors (EL), may also be used for heat transfer. An optimum design interconnects the TL'S and EL's into a functional whole, a thermal management network. With a certain technique, which could be called pocket groove technique, "cooling channels" of a type may be created. Such thermoconductors may be included in the electric layout, so that a thermal layout is superimposed on the connection layout (TL/EL network). Heat distribution and transfer may thus be calculated and optimized by a computer in the same way as the electric distribution by the conductive strips, i.e. the known electric layout, which is produced by a computer-assisted process.

公开(公告)号：WO2009046428A3

公开(公告)日：2009-07-16

申请号：PCT/US2008078959

申请日：2008-10-06

Applicant: BATTERY BIZ INC ,  MARTEN VICTOR ,  PATEL AAKAR ,  VANSTONE MARK

Inventor： MARTEN VICTOR ,  PATEL AAKAR ,  VANSTONE MARK

IPC: H01F5/00

CPC classification number: H05K3/363 ,  H05K1/165 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/096 ,  H05K2201/10303 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49165

Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.

Abstract translation: 本公开涉及使用相对较小的空间并提供低电阻连接来将平面电感部件的绕组PCB高效端接到主PCB。 所公开的方法特别适用于其中几个绕组PCB和/或绕组PCB和主PCB全部被磁路部件包围的平面结构。 该方法允许卷绕PCB简单地放置在主PCB或其他卷绕PCB上，没有任何间隙。 本发明采用配对组的导电环形环与可选的互锁终端引脚，其允许两个PCB固定地耦合在一起，同时保留两个PCB的焊料掩模层之间的最小距离，以防止形成不需要的电连接 两个PCB之间。 焊接用于确保在配对的圆环和可选端子引脚的每个组件中的有效耦合。

公开(公告)号：WO2009046428A2

公开(公告)日：2009-04-09

申请号：PCT/US2008/078959

申请日：2008-10-06

Applicant: BATTERY-BIZ? INC. ,  MARTEN, Victor ,  PATEL, Aakar ,  VANSTONE, Mark

Inventor： MARTEN, Victor ,  PATEL, Aakar ,  VANSTONE, Mark

IPC: H01F5/00

CPC classification number: H05K3/363 ,  H05K1/165 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/096 ,  H05K2201/10303 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49165

Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.

Abstract translation: 本公开涉及使用相对较小的空间并提供低电阻连接将平面感应元件的绕组PCB有效地端接到主PCB。 所公开的方法特别适用于其中几个绕组PCB，和/或绕组PCB和主PCB都由磁路部件封闭的平面结构。 这些方法允许绕组PCB简单地搁置在主PCB或其他绕组PCB上，没有任何间隙。 本公开采用配套的导电环形环，其具有可选的互锁端子销，其允许两个PCB固定地耦合在一起，同时保持两个PCB的焊接掩模层之间的最小距离，以防止形成不需要的电连接 在两个PCB之间。 焊接用于确保配合环形圈和可选端子销的每个组件中的有效耦合。