公开(公告)号：JPH0817849A

公开(公告)日：1996-01-19

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: PURPOSE: To reduce the manufacturing process of the channel region of a basic function unit and to reduce the ON resistance of a power device by forming the deep body part and the channel part of a body region only by ion implantation without performing any thermal diffusion treatment. CONSTITUTION: After a first dopant is selectively ion-implanted into a heavily doped part 5 in a direction that orthogonally crosses a semiconductor surface with a proper amount of dosage and an energy of ion implantation with an insulation gate layer 8 as a mask, a second dopant is selectively ion-implanted into a region 6 along a direction that is inclined at a prescribed angle in an orthogonally crossed direction, thus forming a body region 2. Then, a large dosage of third dopant is ion-implanted into the greatly doped part 5 to form a source region 7 that is nearly aligned to the edge part of the insulation gate layer 8, thus reducing the manufacturing process of the channel region of a basic function unit since no thermal diffusion treatment is made and reducing the on resistance of a power device.

公开(公告)号：JPH07326953A

公开(公告)日：1995-12-12

申请号：JP15230995

申请日：1995-05-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： FURANCHIESUKO PURUBIRENTEI ,  GUREGORIO BONTENPO ,  ROBERUTO GARIBORUDEI

IPC: H03K17/567 ,  H03G1/00 ,  H03K17/00 ,  H03K17/042 ,  H03K17/16 ,  H03K17/687

Abstract: PURPOSE: To optimize power consumption and switching delay by changing the operational condition of an output power transistor(TR) and attaining current absorption in accordance with a current level transmitted by a driving operational amplifier. CONSTITUTION: The driving operational amplifier 15 constituted of a differential input stage consisting of current mirrors 1 to 3 constituting a final stage, a differential TR pair N1 , N2 and a current oscillator IP. The single ends of these mirrors 1 to 3 are directly connected to the gate of the output power TR PW and the current absorption of output currents having the same level on the differential input stage is reduced in accordance with a mirror ratio. An output current from the amplifier is modulated by circuit arrangement consisting of TRs M1 , M2 , P1 to P4 , and an auxiliary current oscillator I while relating to the operation state of the circuit and the TR pair M1 , M2 is cross- coupled with the TR pair N1 , N2 . Thus a current necessary for the charging and discharging the gate node of the TR PW1 is transmitted from the operational amplifier.

公开(公告)号：JPH07321214A

公开(公告)日：1995-12-08

申请号：JP12146895

申请日：1995-05-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/088 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/06

Abstract: PURPOSE: To integrate power integrated circuit structures each having a driving and controlling circuit with an N and a P channel MOSFETs. CONSTITUTION: A power integrated circuit(PIC) structure has an N-type small doped semiconductor layer 2 and a large doped layer substrate 3 lower than the semiconductor layer 2. Power stages and driving and controlling circuits are integrated in the structure 3. Each power stage has a P-type large doped main body region 4 and a small doped main body region 5, and the driving and controlling circuit is provided with a P-type buried region 12 and a P-type large doped annular region 13 extending from a top face of the small doped N-type layer 2 to the buried region 12 and defining an N-type small doped region in a lateral direction. The driving and controlling circuit is completely surrounded by the P-type separation regions 12, 13. Moreover, the driving and controlling circuit has an N channel and a P channel MOSFETs formed respectively in an N-type and a P-type well regions 14, 15 included in the small doped region separated from the small doped layer 2. The annular region 13 and main body region 4 have the same depth to the top face of the small doped layer.

公开(公告)号：JPH07319704A

公开(公告)日：1995-12-08

申请号：JP11600195

申请日：1995-05-15

Applicant: CONS RIC MICROELETTRONICA

Inventor： BIAJIYO JIYAKAROONE ,  BUINCHIENTSUO KATANIA ,  KURAUDEIO RUTSUTSUI ,  BUINCHIENTSUO MATORANGA

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20

Abstract: PURPOSE: To provide a parallel processing method and the circuit constitution for many fuzzy rules independent of the premise part of a rule or the number of terms constituting a logical operator connecting the rules. CONSTITUTION: An inference unit 1 includes plural same inference processing lines 2 having a module structure which are connected in parallel between a data bus and a connecting block 19, and each includes an evaluation block 3, calculation block 4, and consequent part processing block 5 in a belonging relation, and those blocks 3, 4, and 5 are serially connected.

公开(公告)号：JPH07319703A

公开(公告)日：1995-12-08

申请号：JP11600095

申请日：1995-05-15

Applicant: CONS RIC MICROELETTRONICA

Inventor： BUINCHIENTSUO MATORANGA ,  BIAJIYO JIYAKAROONE ,  MATSUSHIMO ABURUZETSUSE

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20

Abstract: PURPOSE: To operate the simultaneous processing of several rules for designing a fuzzy logic by relating a logical operator with the maximum and minimum operation, and completely calculating the full levels of the truth of a rule as the maximum value or the minimum value of N pieces of partial true levels. CONSTITUTION: Four same circuits 2 are provided inside an inference unit 1, and each circuit 2 is provided with two input terminals 11 and 12 and an output terminal O. The input terminal 11 receives one set of data ALFA, each ALFA are encoded by 16 bits, and the data has the value of weight to be processed. The input terminal 12 receives one set of logical operators OPC, and those OPC are encoded by 3 bits for a logical operation to be executed. This logical operator OPC is made correspond to the maximum and minimum fuzzy logical operation, and an inference rule value OMEGA is supplied to the output terminal O. Then, the full levels of the truth of a rule is calculated based on a partial true model from the value OMEGA, and a parallel processing is operated.

公开(公告)号：JPH07295667A

公开(公告)日：1995-11-10

申请号：JP32961594

申请日：1994-12-02

Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

Inventor： SCACCIANOCE SALVATORE ,  PALARA SERGIO ,  AIELLO NATALE

IPC: G05F3/30

Abstract: PURPOSE: To provide a circuit that generates a reference voltage with negative temperature coefficient together with a band gap reference voltage with positive temperature coefficient. CONSTITUTION: This circuit includes a network consisting of a Vbe voltage multiplier circuit (K'Vbe) circulating a properly stabilized current against change in a supply voltage between an output node A of an amplifier and a band gap voltage generating network, at least one resistor R connected between a band gap voltage node and ground, and resistive voltage dividers R1, R2 connected to between an output node and ground.

公开(公告)号：JPH07226514A

公开(公告)日：1995-08-22

申请号：JP895795

申请日：1995-01-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： PIEERO JIORUJIO FUARIIKA

IPC: H01L27/06 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/78

Abstract: PURPOSE: To realize a high conductivity IGBT integrated structure by which a punch- through between a body region and a substrate can be avoided and the conductivity modulation of an epitaxial drain region is not limited too much. CONSTITUTION: A high conductivity IGBT integrated structure has a 1st conductivity type heavily doped semiconductor 1 of which the 1st electrode of the IGBT consists, a 2nd conductivity type lightly doped semiconductor layer 6 which is piled on the substrate 1, at least one 1st conductivity type 1st doped region (7-8) which is extended from the top surface of the semiconductor layer 6 to the inside of the layer 6 and of which the channel region of the IGBT consists and a 2nd conductivity type 2nd doped region 9 which is extended from the top surface of the semiconductor layer 6 to the region (7-8). With this constitution, a semiconductor material buried layer (2-5) is formed between the substrate 1 and the semiconductor layer 6 and, further, composed of 2nd conductivity type heavily doped regions 5 and 2nd conductivity type lightly doped regions 2 which are inserted between the regions 5. In order to prevent the depletion layer of a junction between the region (7-8) and the semiconductor layer 6 from reaching the substrate, a distance between the two successive regions 5 is approximately equal to the thickness of the region 5 practically.

公开(公告)号：JPH07142524A

公开(公告)日：1995-06-02

申请号：JP14487094

申请日：1994-06-27

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ANTONIO GURATSUSO ,  ANNTONIO PINTO

IPC: H01L21/60 ,  B23K20/00 ,  H01L21/607

Abstract: PURPOSE: To improve the quality of connecting part between a semiconductor circuit chip and the pin of its supporting frame by forming a pair of grooves at least at the working terminal of bonding top end and making the lengths of grooves different. CONSTITUTION: In order to improve the quality and validity of connecting part to be bonded, working is started from the assumption that a bonding zone is to be expanded. A tool 9 for bonding having a working terminal 12 formed from a pair of grooves 13 and 14 at least with different lengths is prepared. Besides, one terminal of wire 7 on a terminal connector 5 is held in the 1st groove 13 and bonded to the terminal connector 5. Further, the other terminal of wire 7 on a semiconductor chip 1 is held in the 2nd groove 14 and bonded to the semiconductor circuit chip 1. Thus, even at the time when the wire 7 is to be cut by sharp pulling so as to be ordinarily applied to a thin wire, it is bonded and no damage is applied to the joint.

公开(公告)号：JPH07141183A

公开(公告)日：1995-06-02

申请号：JP12539794

申请日：1994-06-07

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： BIAJIYO RUTSUSO ,  RINARUDO PORUTSUTSUI ,  KURAUDEIO RUTSUTSUI

IPC: G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04

Abstract: PURPOSE: To minimize the size of a storage part and to perform an operation at a high calculation speed and at the excellent degree of a resolution by limiting the storage of a belonging relation function corresponding to a point where the value of the degree of the belonging relation of a function is not zero (not null) in a discussion area. CONSTITUTION: Signals from a system 9 to be controlled are converted to fuzzy logic information by a conversion device 2 and then sent to the storage part 5A and the specified storage of only a part of the information is executed there. The size of the storage part 5A is decided in response to the number of the non-zero values of the belonging relation function f (m) at the prescribed point (m) of the discussion area U provided with the maximum number of a non-null value and is far more compact than the size of the storage part obtained by a conventional method. The information stored in the storage part 5A is sent to a buffer part 8 and the restoration of the fuzzy logic information to be used in a calculation part 6 for an appropriate inference operation is implemented there. Thus, while minimizing a required storage capacity for a hardware, the operation is performed at the high calculation speed and at the high degree of the resolution.

公开(公告)号：JPH06295954A

公开(公告)日：1994-10-21

申请号：JP23483693

申请日：1993-09-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： CHIRINO RAPISARUDA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

Abstract: PURPOSE: To provide a method of removing bird beaks from the selective diffusion of semiconductor elements having a semiconductor substrate having recesses blocked by at least one vertical wall for growing insulation regions covered with an oxide pad layer and then with a first nitride layer. CONSTITUTION: The method comprises steps of selectively etching an oxide layer 2 in recesses to define peripheral recesses 6, 8 between a semiconductor substrate 1 and nitride, filling the recesses 6, 8 with a nitride, and growing an oxide in the recesses to form insulation regions contrasted to nitride parts 9, 10 closing the recesses 6, 8.